EECS314_W08_HW10_p1

# EECS314_W08_HW10_p1 - EECS 314 Winter 2008 Homework set 10...

This preview shows pages 1–4. Sign up to view the full content.

EECS 314 Winter 2008 Homework set 10 Student’s name ___________________________ Discussion section # _______ (Last, First, write legibly, use ink) (use ink) Instructor is not responsible for grading and entering scores for HW papers lacking clear information in the required fields above © 2008 Alexander Ganago Page 1 of 2 Scores for the HW set: Problem 1 2 3 4 5 6 7 Total Score Problem 1 Combinations of Logic Gates The Big Picture М arious logic gates can be built of NAND gates. In this problem you will prove that certain combinations of NAND gates do indeed operate as specific logic gates, already known to you. The Assignment Part 1 (10 points) Consider the combination of NAND gates shown here: Prove that it acts as the OR gate, that is other words, it performs the same logic operation on any combination of the two inputs A and B as the gate OR does. Use the truth table of OR, reproduced here for your convenience; fill in the blank table (on the left), and compare it with the given table for OR. If the two truth tables are identical, the logic operations are identical. Show your work on additional pages. Part 1 2 3 Total

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
EECS 314 Winter 2008 Homework set 10 Student’s name ___________________________ Discussion section # _______ (Last, First, write legibly, use ink) (use ink) Instructor is not responsible for grading and entering scores for HW papers lacking clear information in the required fields above © 2008 Alexander Ganago Page 2 of 2 Problem 1, continued Part 2 (10 points) Repeat for the NOR operation. Show your work on additional pages. Part 3 (20 points) This diagram shows a combination of NOR gates, which acts as a logic gate. Determine its type. A. AND B. OR C. NAND D. NOR E. None of the above. Show your work on additional pages.
EECS 314 Winter 2008 Homework set 10 Student’s name ___________________________ Discussion section # _______ (Last, First, write legibly, use ink) (use ink) Instructor is not responsible for grading and entering scores for HW papers lacking clear information in the required fields above © 2008 Alexander Ganago Page 1 of 2 Problem 2 Digital Circuits with Memory: Set-Reset The Big Picture The circuit shown on this diagram is called SR flip-flop, where SR stands for Set-Reset. On the left, it is shown as a pair of NOR gates; on the right, the same circuit is shown as a functional block. The two outputs are logic complements of each other: if Q equals “1” then Q _ equals “0” and vice versa . The inputs R and S are not allowed to equal “1” at the same time; if both inputs equal “0” then the output Q is kept in its previous state indefinitely (while the power is applied to the circuit), which makes it a simple memory cell. One of the practical applications of this circuit is to avoid the

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 12

EECS314_W08_HW10_p1 - EECS 314 Winter 2008 Homework set 10...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online