l18 - Processor Datapath Simple subset: addu addiu subu or...

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Unformatted text preview: Processor Datapath Simple subset: addu addiu subu or ori lw sw beq j Storage Elements For the MIPS, storage elements specied by the ISA: memory (instructions and data) 32 32-bit registers program counter Register 0 is always zero. We've already seen how to design a single register with a write enable. Register File The MIPS register le contains: 32 32-bit registers (register 0 special) One write bus + write enable Two read buses Register selection inputs 32 32 32 1 5 5 5 file register CLK WE RW RA RB B A W Register File: Timing Reads are combinational Writes occur on the negative edge of the clock if WE is high Implementation: Standard solution: use mux/demux Tri-state outputs _xt x xe Memory One address bus (32-bit) Two data buses (32-bit) Two-bit memory control input Memory interface doesn't wait for the clock 1 1 => write word addr mc 0 0 => read 0 1 => write byte 1 0 => write halfword din 32 32 2 32 dout memory Memory...
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l18 - Processor Datapath Simple subset: addu addiu subu or...

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