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l21 - Memory Design Memory can be built in different ways...

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Unformatted text preview: Memory Design Memory can be built in different ways... • Dynamic (DRAM): leaky, has to be refreshed periodically • Static (SRAM) Memory access latency: • DRAM: 50-70ns, larger memory size (can t more in a given area) • SRAM: 3-10ns, smaller memory size CPU clock cycle time: 0.5-2ns Processor-Memory Gap Current trends: Component Capacity Speed Transistors/logic 1.4x each year 2x in 3 years DRAM 4x in 3 years 1.4x in 10 years Disk 4x in 3 years 1.4x in 10 years The gap between processor speed and memory speed is growing. CPI Equation Suppose: 60ns DRAM, 500MHz CPU. Instruction mix: ALU: 50%, load/store: 30%, branch: 20% Assume branch delay slots are all lled with nop s. MIPS CPI: . 5 × 1 + 0 . 2 × 2 + 0 . 3 × 30 ⇒ 9 . 9 ! Problem: memory is too slow. Speeding Up Memory Access Basic idea: • Build a small, fast memory ( cache ) • Use to store frequently accessed blocks of memory • When it lls up, discard some blocks and replace them with others • Works well if we are reusing data blocks Examples: incrementing a variable, loops, function calls, etc. Locality Principles Temporal Locality • the location of a memory reference is likely to be...
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