Finite state machine

Finite state machine - Chapter #8: Finite State Machine...

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No. 8-1 Chapter #8: Finite State Machine Design
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No. 8-2 Counters: Sequential Circuits where State = Output Generalizes to Finite State Machines: Outputs are Function of State (and Inputs) Next States are Functions of State and Inputs Used to implement circuits that control other circuits "Decision Making" logic Application of Sequential Logic Design Techniques Word Problems Mapping into formal representations of FSM behavior Case Studies
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No. 8-3 Concept of the State Machine Partitioning into Datapath and Control When Inputs are Sampled and Outputs Asserted Basic Design Approach Six Step Design Process Alternative State Machine Representations State Diagram, ASM Notation, VHDL, ABEL Description Language Moore and Mealy Machines Definitions, Implementation Examples Word Problems Case Studies
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No. 8-4 Computer Hardware = Datapath + Control Registers Combinational Functional Units (e.g., ALU) Busses FSM generating sequences of control signals Instructs datapath what to do next "Puppet" "Puppeteer who pulls the strings" Qualifiers Control Control Datapath State Control Signal Outputs Qualifiers and Inputs
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No. 8-5 Example: Odd Parity Checker Even [0] Odd [1] Reset 0 0 1 1 Assert output whenever input bit stream has odd # of 1's State Diagram Present State Even Even Odd Odd Input 0 1 0 1 Next State Even Odd Odd Even Output 0 0 1 1 Symbolic State Transition Table Output 0 0 1 1 Next State 0 1 1 0 Input 0 1 0 1 Present State 0 0 1 1 Encoded State Transition Table
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No. 8-6 Example: Odd Parity Checker Next State/Output Functions NS = PS xor PI; OUT = PS D R Q Q Input CLK PS/Output \Reset NS D FF Implementation T R Q Q Input CLK Output \Reset T FF Implementation Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0 Clk Output Input 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 1 1
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No. 8-7 Timing: When are inputs sampled, next state computed, outputs asserted? State Time: Time between clocking events Clocking event causes state/outputs to transition, based on inputs For set-up/hold time considerations: Inputs should be stable before clocking event After propagation delay, Next State entered, Outputs are stable NOTE: Asynchronous signals take effect immediately Synchronous signals take effect at the next clocking event E.g., tri-state enable: effective immediately sync. counter clear: effective at next clock event
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No. 8-8 Example: Positive Edge Triggered Synchronous System On rising edge, inputs sampled outputs, next state computed After propagation delay, outputs and next state become stable Immediate Outputs: affect datapath immediately could cause inputs from datapath to change Delayed Outputs: take effect on next clock edge propagation delays must exceed hold times Outputs State T ime Clock Inputs
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No. 8-9 Communicating State Machines Fragment state diagrams Initial inputs/outputs: X = 0, Y = 0 One machine's output is another machine's input CLK FSM 1 X FSM 2 Y A A B C D D FSM 1 FSM 2 X Y A [1] B [0] Y=0 Y=1 Y=0,1 Y=0 C [0] D [1] X=0 X=1 X=0 X=0 X=1
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No. 8- Six Step Process 1. Understand the statement of the Specification
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This note was uploaded on 09/10/2008 for the course CSIS 2810 taught by Professor Balasa during the Spring '08 term at Southern Utah.

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Finite state machine - Chapter #8: Finite State Machine...

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