Memory_Design - VLSI Memory Design Shmuel Wimer Bar Ilan...

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August 2010 1 VLSI Memory Design Shmuel Wimer Bar Ilan University, School of Engineering
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August 2010 2 A memory has 2 n words of 2 m bits each. Usually 2 n >> 2 m , (e.g. 1M Vs. 64) which will result a very tall structure. The array is therefore folded into 2 n-k rows, each containing 2 k words, namely, every row contains 2 m+k bits. Consider 8-words of 4-bit memory. We’d like to organize it in 4 lines and 8 columns. The memory is folded into 4- word by 8-bit, so n=3, m=2 and k=1. Larger memories are built from smaller sub-arrays to maintain short word and bit lines.
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August 2010 3 Word-lines Bit-lines Bit-line Conditioning R o w D e c o d e r Column Decoder Column Circuitry Array of 2 n x2 m cells, organized in 2 n-k rows by 2 m+k columns 2 m bits n-k n k General Memory architecture 4-word by 8-bit folded memory
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August 2010 4 12-Transistor SRAM Cell When write=1 the value at the bit is passed to the middle inverter while the upper tri-state inverter is in high Z. Once write=0 the upper and the center inverters are connected in a positive feedback loop to retain cell’s value as long as write=0. write write read read bit The value of bit-line needs to override the value stored at the cell. It requires careful design of transistor size for proper operation.
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August 2010 5 12-Transistor SRAM Cell write write read read bit When read=1 the output of the lower tri-state inverter gets connected to the bit so cell’s value appears on the bit-line. The bit-line is first pre- charged to one, so only if the value stored at cell is zero the bit-line is pulled down.
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August 2010 6 Though robust, 12-transistor cell consumes large area. Since it dominates the SRAM area, a 6-transistor is proposed, where some of the expense is charged on the peripheral circuits. 6-Transistor SRAM Cell bit bit word
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August 2010 7 Layout of IBM 0.18u SRAM cell Layout design Lithography simulation Silicon
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August 2010 8 SRAM operation is divided into two phases called Φ1 and Φ2, which can be obtained by clk and its complement. Read Write Operations bit bit word P1 P2 N1 N2 N4 N3 A A Pre-charge both bit-lines high. Turn on word-line. One of the bit-lines must be pulled-down. Since bit-line was high, the 0 node will go positive for a short time, but must not go too high to avoid cell switch. This is called read stability .
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August 2010 9 Read Stabilit y bit A A must remain below threshold, otherwise cell may flip. Therefore N1>>N2.
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August 2010 10 Weak Medium Strong Let A=0 and assume that we write 1 into cell. In that case bit is pre-charged high and its complement should be pulled down. It follows from read stability that N1>>N2 hence A=1 cannot be enforced through N2. Hence A complement must be enforced through N4, implying N4>>P2. This constraint is called writability .
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