SPnRtutorial - ASIC Design Methodology using Cadence SP&R...

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ASIC Design Methodology using Cadence SP&R Flow (Information about PKS-SE and ASIC design flow borrowed from Cadence documents.) 1 ASIC Design Methodology ........................................................................................... 2 1.1 Front End Tasks ...................................................................................................... 2 1.2 Back End Tasks: Physical implementation ............................................................. 3 2 A Few Basic Concepts .................................................................................................. 4 3 Commonly Used Acronyms .......................................................................................... 9 4 Information about Library Files .................................................................................. 10 5 Directory Structure ...................................................................................................... 12 6 RTL Synthesis ............................................................................................................. 13 6.1 Creating a Flattened Netlist .................................................................................. 20 7 FloorPlanning .............................................................................................................. 22 8 Port Placement ............................................................................................................ 23 9 Constraints .................................................................................................................. 24 9.1 Defining a New Ideal Clock ................................................................................. 24 9.2 Binding a Port to a Clock ..................................................................................... 24 9.3 Setting Constraints through a Script File ............................................................. 26 10 Optimize the design ................................................................................................. 28 10.1 Navigating through the optimized schematic ....................................................... 28 10.2 H i ghlight the critical path ..................................................................................... 28 10.3 Generating Reports ............................................................................................... 29 11 Clock Tree Generation (CTPKS) ............................................................................. 32 12 Post Clock Tree Optimization .................................................................................. 32 13 Global Routing ......................................................................................................... 32 14 Detailed Routing ...................................................................................................... 32 15 Post Route In Place Optimization ............................................................................ 32 16 Sample Script for Entire Process ............................................................................. 32 17 Reference Documents .............................................................................................. 32 1
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1 ASIC Design Methodology The tasks involved in ASIC design are usually split up into two sections: Front End tasks and Back end tasks, as shown in the following diagram: Figure 1. ASIC Design Stages 1.1 Front End Tasks Front-end means the design conducted by the ASIC designers, which usually includes HDL description; Simulation and Functional verification; Synthesis (net list). This step is finished by the ASIC sign-off point, so that the verified design will be delivered to the ASIC foundry. The following diagram illustrates the tasks of front-end design. Figure 2. Front End Design Tasks 2
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1.2 Back End Tasks: Physical implementation Back-end tasks are conducted by the foundry, which usually includes Power Rail Design; Clock Tree generation; Congestion reduction; Placement and Route; I/O and block Placement; Coupling; Hot spots; DRC. However, the overall timing and functional requirements are actually defined in the previous front-end phase so that the back-end phase will make sure after finishing back-end tasks, timing and functionalities will be the same. The following diagram illustrates the back-end phase: Figure 3. Back End Design Tasks In our design methodology, we will be using Cadence’s Physically Knowledgeable Synthesis (PKS) and Silicon Ensemble (SE) to perform all the tasks of ASIC design. The following figure gives an idea about the tasks performed in each of the tools. Figure 4. SP & R Flow in Cadence Tools 3
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2 A Few Basic Concepts There are various terms used during the steps of the ASIC design methodology that need to be understood properly before proceeding with the ASIC design. This section explains many of the basic concepts that are involved in every stage of the design. In the floorplanning stage , the logical netlist is mapped to the physical floorplan. The goal of chip floorplanning is to: Partition the design into physical sub-blocks.
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