(chapter 1) FLIP-FLOPS

# (chapter 1) FLIP-FLOPS - TEL21604 DIGITAL LOGIC DESIGN...

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TEL21604 DIGITAL LOGIC DESIGN CHAPTER 1

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FLIP-FLOPS AND RELATED DEVICES Types of Flip-Flops: - R-S flip-flops - D flip-flops - J-K flip-flops Edge Triggered Flip Flop
Course Learning Outcome Design the counter and register circuit by using the flip flop theory.

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SR Flip Flop Data storage circuit that constructed using basic gates such as NOR and NAND gates. The operation is by placing (1) HIGH on the SET and a 0 (LOW) on RESET. That should make Q is (1) HIGH and NQ is (0) LOW. ------- (SET condition)
SET condition

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RESET condition
Truth Table SR FF

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Symbol SR Flip Flop
Example SR Flip Flop

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SR FF Application
Edge Triggered J-K Flip-Flops Flip flop accepts data only on the J and K inputs that present at the active clock edge. J representing “S” and K representing “R” . When J is HIGH(1), means SET condition. When K is HIGH(1), means RESET condition.

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Symbol +VE Edge Triggered
Symbol –VE Edge Triggered

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HIGH to LOW
Truth Table –VE Edge Triggered JKFF

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Symbol of –VE Edge Triggered JKFF
Timing Diagram –VE Edge Triggered JKFF

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Edge Triggered JK flip-flop Versatile and is widely used type of flip-flop.
• Fall '15
• professor
• Clock signal, Logic gate, Jitter

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