Digital Lecture 12

# Digital Lecture 12 - 17-Feb-064:35 PM Sequential Logic FFs EEL 3701 EEL 3701 Menu Part 2 of 3701 Sequential Digital Machines Latches and Flip-Flops

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17-Feb-06—4:35 PM 1 1 University of Florida, EEL 3701 – File 12 © Drs. Schwartz & Arroyo Sequential Logic, FFs EEL 3701 1 University of Florida, EEL 3701 – File 12 © Drs. Schwartz & Arroyo EEL 3701 Menu Part 2 of 3701: Sequential Digital Machines • Latches and Flip-Flops: >S-R latches >D latches >T latches Look into my . .. EEL 3701 2 University of Florida, EEL 3701 – File 12 © Drs. Schwartz & Arroyo EEL 3701 Topic 2 : Sequential Digital Machines or Sequential Logic SLIDE from Lecture #2 SLIDE from Lecture #2 Comb. Logic Network Memory Memory Q Q + n m k k XY Y = G(Q,X), There are m equations or m scalar functions. Each Q is called a state a summary of the past or historical behavior. Q + = F(Q,X), There are k equations or k scalar functions.

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17-Feb-06—4:35 PM 2 2 University of Florida, EEL 3701 – File 12 © Drs. Schwartz & Arroyo Sequential Logic, FFs EEL 3701 3 University of Florida, EEL 3701 – File 12 © Drs. Schwartz & Arroyo EEL 3701 Sequential Logic and Memory • General Model Combinational Logic Memory X Y QQ + • Observation: All circuits so far have had no feedback. • What happens if we add feedback? Z = H L H L Z = L H L H Z Z t Q + = F(Q,X) Y = G(Q,X) 3_Nots.cct >f 20MHz >We call this a “un-gated” oscillator or clock >Z turns on & off >Go to LogicWorks (stick/unstick) EEL 3701 4 University of Florida, EEL 3701 – File 12 © Drs. Schwartz & Arroyo EEL 3701 Gated-Oscillators • Consider what happens if we replace the first Level-Shifter with a NAND gate • We call this a “gated-” oscillator or clock • X turns it on & off >Go to LogicWorks Y X When X=1 Y t Gated_Osc.cct • Note that the circuit is stable! • What if we connect the following circuit Z
17-Feb-06—4:35 PM 3 3 University of Florida, EEL 3701 – File 12 © Drs. Schwartz & Arroyo Sequential Logic, FFs EEL 3701 5 University of Florida, EEL 3701 – File 12 © Drs. Schwartz & Arroyo EEL 3701 Consider the following circuit: Latch: The Beginning z 1 x 0 x 1 z 0 z 1 z 0 z 1 LLLHHHH LLHHL LHLHHLH LHHHL HLLHH HLHHLHL HHLLH HHHLH Tracing through the circuit: z 1 = /x 1 + x 0 z 1 K-Map for z 1 (everything active-high) x 0 z 1 x 0 x 1 z 1 01 00 1 1 0 0 11 0 1 10 /x 1 • This device is called a latch or “Flip- Flop.” It flip flops between 2 states.

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## This note was uploaded on 09/11/2008 for the course EEL 3701c taught by Professor Gugel during the Spring '05 term at University of Florida.

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Digital Lecture 12 - 17-Feb-064:35 PM Sequential Logic FFs EEL 3701 EEL 3701 Menu Part 2 of 3701 Sequential Digital Machines Latches and Flip-Flops

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