Digital Lecture 13 - 1-Mar-0610:18 AM J-K FF, Counters EEL...

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1-Mar-06—10:18 AM 1 1 University of Florida, EEL 3701 – File 13 © Drs. Schwartz & Arroyo J-K FF, Counters EEL 3701 1 University of Florida, EEL 3701 – File 13 © Drs. Schwartz & Arroyo EEL 3701 Menu • Clocks and Master-Slave Flip-Flops • J-K and other Flip-Flops • Truth table & excitation table • Adders (see [Lam: pg 130]) • Counters Look into my . .. EEL 3701 2 University of Florida, EEL 3701 – File 13 © Drs. Schwartz & Arroyo EEL 3701 Master-Slave Flip-Flop ALU etc. t c = time when signals change t w = digital systems do their work here, others finish their work in this phase ± Most digital systems expect their inputs to be stable very early in the t c phase of the clock. As drawn, it is possible for S and/or R to “change” while CLK = 1 (during t c ). Master-Slave Latch/Flip-Flop Q (active-high and -low) may change during time t c even though other hardware expect them to be stable!! CLK t c t w S R Q Q E CLK
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1-Mar-06—10:18 AM 2 2 University of Florida, EEL 3701 – File 13 © Drs. Schwartz & Arroyo J-K FF, Counters EEL 3701 3 University of Florida, EEL 3701 – File 13 © Drs. Schwartz & Arroyo EEL 3701 Master-Slave Flip-Flop Q: How do we solve this problem? A: Use 2 latch’s, one master , one slave . Signals do not change during t c . (This is a digital-only solution; the 3 rd option discussed earlier.) Q: Why? A: Now {Q(H), Q(L)} will not change until t w . Hence, inputs to other systems are stable during t c . Master Slave S R Q Q E S R Q Q E CLK t c t w CLK t c t w Master Master -Slave S Slave S -R Flip R Flip -Flop Flop EEL 3701 4 University of Florida, EEL 3701 – File 13 © Drs. Schwartz & Arroyo EEL 3701 Flip-Flops in LogicWorks • In LogicWorks: >The “D Flip Flop” has a rising edge clock >The “JK Flip Flop” has a falling edge clock >The “T Flip Flop” has a falling edge clock >The “D Flip Flop En n.i. RS” has a rising edge clock >The “D Flip Flop En wo/SQ/” has a rising edge clock >The “D Flip Flop En wo/RSQ/” has a rising edge clock >The “D Flip Flop En wo/SQ/” has a rising edge clock >The “JK Flip Flop n.i. RS” has a falling edge clock ASSUME NOTHING LW_FFs.cct
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1-Mar-06—10:18 AM 3 3 University of Florida, EEL 3701 – File 13 © Drs. Schwartz & Arroyo J-K FF, Counters EEL 3701 5 University of Florida, EEL 3701 – File 13 © Drs. Schwartz & Arroyo EEL 3701 Master-Slave JK FF Gated S-R Latch Q(L) Q(H) S(H) E(H) Pre-Clear Pre-Set R(H) S R Q Q E LogicWorks > With master-slave FFs we have a completely digital solution to the “stable” input problem. No oscillation occurs!!!! JK_from_M-S_SR*.cct Master-Slave J-K FF (Falling Edge Clock) R Q E R Q E Master Slave QQ S S K J J-K FF with falling edge-clock J K Q Q S R EEL 3701 6 University of Florida, EEL 3701 – File 13 © Drs. Schwartz & Arroyo EEL 3701 Flip-Flops Master-Slave J-K FF (Rising Edge Clock) J-K FF with rising edge-clock J K Q Q K Q E K Q E Master Slave JJ T-FF using JK D-FF using JK T J K Q Q D J K Q Q D-FF using SR D S R Q Q How about constructing a JK with a D?
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Digital Lecture 13 - 1-Mar-0610:18 AM J-K FF, Counters EEL...

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