Midterm 01 - solution

Midterm 01 - solution - NAME: ; SID #: . EEE 333, ASU...

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NAME: ; SID #: . EEE 333: Spring 2008, Midterm – 01 1 EEE 333, ASU Spring 2008, Yu (Kevin) Cao Midterm – 01 February 14th, 9:15am-10:30am, PSA 118 NAME: , . SID #: . (LAST) (FIRST) Problem 1: (15) . Problem 2: (23) . Problem 3: (12) . Total (50) . Solution
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NAME: ; SID #: . EEE 333: Spring 2008, Midterm – 01 2 Problem 1: VHDL Basics (15 pts) Please select the right answer for each question below. a. A VHDL model that exclusively uses concurrent signal assignment statements to describe the functionality of the design most likely represents which of the following styles? Ñ behavioral Ñ data flow Ñ structural b. Which of the following is NOT a VHDL data object? Ñ signal Ñ variable Ñ wire Ñ constant c. Which of the following statements is true? Ñ All VHDL processes execute concurrently. Ñ Concurrent signal assignment statements are one-line processes. Ñ Statements in a process execute sequentially. Ñ
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This note was uploaded on 09/29/2008 for the course ECE 333 taught by Professor Cao during the Spring '08 term at ASU.

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Midterm 01 - solution - NAME: ; SID #: . EEE 333, ASU...

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