EEE333 MidtermII sheet

EEE333 MidtermII sheet - Midterm II Review Highlights...

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Midterm II Review Highlights Sequential logic Finite State Machine Testbenches and effective coding skills Combinational vs. Sequential Combinational: output is a function of present inputs (no memory) Sequential: output is also dependent on previous states (need memory to store data) Combinational: Output = f (In) Sequential: Output = f (In, Previous state) Process Statements Syntax of Process process_label: process [(sensitivity_list)] is process_declarations begin sequential statement end process [process_label]; The process sensitivity list is an implicit “wait on sensitivity_list” at the end You can’t use both but must have one – otherwise the process will never be activated! . Process can describe a logic block Outputs driven by a process can only be driven by that process An implicit key point: you need to think about how signals will be initialized or have their states changed on events Process Execution Model Executes once (at time = 0) runs until it hits a WAIT statement . Time advances until the wait condition is satisfied Execution resumes only then . Executes in an endless loop Interrupted only by wait statements The bottom of the process contains an implicit “go to the top” This makes it model hardware, which waits for inputs to change to do anything new Time does not advance within a process; it advances during a wait statement only Wait Statements Process advances during a wait statement only If you only want to run once, use wait without the sensitivity list reset_gen: process is begin if extended_reset then reset <= ‘1’, ‘0’ after 200 ns; else reset <= ‘1’, ‘0’ after 50 ns; end if ; wait ; end process reset_gen; A simple testbench usually ends in a “ wait ;” Use “ unaffected ”or “ null ” if you don’t want to modify the variable This implies a latch to remember its state Other Wait Statements wait until boolean_expression; wait for time_expression; There should be only one wait statement in the process How would you translate statements between wait ? Initialization specifications on port and signal declarations are ignored during the synthesis This is to match the hardware property of logic elements . All the behavior preceding the (first and only) wait statement must be translated into logic that produces the correct signal values when the circuit powers up Synthesis tools try to reproduce that behavior Example: D-FF entity D_ff is port (D : in bit; clk : in bit; clr : in bit; Q : out bit); end entity D_ff; architecture behav of D_ff is begin state_change : process (clk, clr) is begin if clr = ‘1’ then Q <= ‘0’ after 2ns; elsif clk’event and clk = ‘1’ then Q <= D after 2ns; end if ; end process state_change; end architecture behav; Delta Delay All signal assignments in VHDL take at least one delta delay This way we avoid non-physical behavior even if no delay is given For instance:
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This note was uploaded on 09/29/2008 for the course ECE 333 taught by Professor Cao during the Spring '08 term at ASU.

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EEE333 MidtermII sheet - Midterm II Review Highlights...

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