{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Lab 5 - the machine Display the machine states on the...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
EEE 333, ASU Spring 2008, Yu (Kevin) Cao Lab #5 Due Friday, April 25 th . The objective of this lab is to practice your FPGA design knowledge. Submission : Submit a file with the VHDL code to the digital drop box. You must demonstrate your work to the TA's first. FPGA Design of Finite-State Machine Implement the following simple state machine on the Spartan-3 FPGA board. Any input not associated with an edge in the diagram keeps the machine in the same state. If two or more switches are asserted, stay in the same state. Generate the clock with pushbutton1 on the board. Implement the debouncing circuits (otherwise you’ll get multiple clocks per button press). The switches should control the inputs to determine the next state of
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: the machine. Display the machine states on the 7-segment displays as: S_00, S_0A, etc. as in the diagram. This is done as a Moore output. Hint: Use the buttons and 7-segment displays on the Spartan-3 board, as explained by the board manual. You might want to set the system up so that the 7-segment displays are directly driven by the switches or buttons to verify that you have the correct polarity and connections before coding the state machine. Use the board clock to get the 7-segment displays to time multiplex properly. Divide the board clock down if needed. Check that your clock is properly de-bounced by making sure that with SW1 = 1 (or SW2 = 1 in other states) that no states are skipped....
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online