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Unformatted text preview: Charles Wong Lab #2 Arithmetic Logic Unit EEE 333 Professor Yu (Kevin) Cao March 5, 2008 Objective The objective of lab exercise #2 is to practice our VHDL coding and the modeling of combinational logic units. We were to model an 8bit Arithmetic / Logic Unit (ALU) using VHDL coding and to create a test bench to simulate the unit and verify the 8bit output and carryout bit for a given two 8bit inputs and a carryin bit. Specifications The ALU inputs are 8bit std_logic_vectors: aluin_a and aluin_b . The output is an 8 bit std_logic_vector: alu_out . The output of the ALU will operate on the inputs A and B depending on the control inputs C in the following manner as stated in the following table: C (3 downto 0) Operation 0000 alu_out = aluin_a + aluin_b 0001 alu_out = aluin_a + aluin_b + Cin 0010 alu_out = aluin_a  aluin_b 0011 alu_out = aluin_a  aluin_b Cin 0100 alu_out = aluin_a logically shifted right by aluin_b 0101 alu_out = aluin_a arithmetic shifted right by aluin_b 0110 alu_out = aluin_a rotated right by aluin_b 0111 alu_out = all 0s 1000 alu_out = aluin_a OR aluin_b (bitwise or) 1001 alu_out = aluin_a AND aluin_b (bitwise and) 1010 alu_out = aluin_a XOR aluin_b (bitwise xor) 1011 alu_out = NOT aluin_a (bitwise inversion) 1100 alu_out = undefined 1101 alu_out = undefined 1110 alu_out = undefined 1111 alu_out = undefined If a carry out is generated, then a setreset latch generating a signal Cout should be set, otherwise it is cleared. If the result is all 0s, then a setreset latch generating a signal zero should be set, otherwise cleared. The test bench should test every operation as well as the Cout and Cin for correct operation. VHDL Coding The code generated for the ALU is:...
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 Spring '08
 Cao

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