Lab#3 - Charles Wong Lab#3 12-bit SRAM with 128 Address Locations EEE 333 Professor Yu(Kevin Cao April 1 2008 Objective The objective of lab

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Charles Wong Lab #3 12-bit SRAM with 128 Address Locations EEE 333 Professor Yu (Kevin) Cao April 1, 2008
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Objective The objective of lab exercise #3 is to practice our VHDL coding and the modeling of memory design and test schemes. We were to model an 12-bit Static Random Access Memory (SRAM) using VHDL coding and to create a test bench to simulate the unit and verify the 12-bit output of the SRAM by testing using 5 pattern memory tests. The architecture should be a state machine to test the design and should write one of five patterns to the entire memory array before reading from the entire memory array and checking that the test pattern is correct. Each pattern should be written and then read from as an entire array. Once all five pattern tests are completed, the machine should go to a PASS state and quit or show a FAIL state and output the failing test and then quit. Specifications The SRAM input is a 12-bit std_logic_vector: Data_in . The 1-bit inputs are the clock , enable, write, and read. The 7-bit std_logic_vector inputs are Read_Addr and Write_Addr . The 12-bit std_logic output is Data_out . The SRAM is an array of 128 memory locations consisting of 12-bit data areas. The enable, read and write control inputs will determine whether the SRAM memory unit is enabled and whether it will read from a memory location or write to a memory location. The address locations for each of the read or write operation is determined by the Read_Addr and the Write_Addr 7-bit inputs. The five test patterns are: 1. All ‘1’s 2. All ‘0’s 3. A “checkerboard pattern. This means location 0 gets “010101010101”, while location 1 gets “101010101010”, and soon, so that the array looks like: 010101010101 101010101010 010101010101 101010101010 4. The opposite checkerboard pattern. The idea is all bits see the same patterns. 5. The address of the location to itself. This test tests whether the memory address decoder works.
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VHDL Coding The code generated for the SRAM is: ------------------------------------------------------------------------------------------ -- Assignment: Lab #2 (ALU) -- Name: Charles Wong -- File: ALU2.vhd ------------------------------------------------------------------------------------------ library IEEE; use ieee.numeric_std.all; use ieee.numeric_bit.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity ALU is port( aluin_a : in std_logic_vector(7 downto 0); aluin_b : in std_logic_vector(7 downto 0); alu_cin : in std_logic; alu_control : in std_logic_vector(3 downto 0); alu_cout : out std_logic; alu_out : out std_logic_vector(7 downto 0) ); end ALU; architecture ALU of ALU is begin process(aluin_a, aluin_b, alu_cin, alu_control) variable output : std_logic_vector(8 downto 0); variable count : std_logic_vector(7 downto 0); begin case alu_control is when "0000" =>
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This note was uploaded on 09/29/2008 for the course ECE 333 taught by Professor Cao during the Spring '08 term at ASU.

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Lab#3 - Charles Wong Lab#3 12-bit SRAM with 128 Address Locations EEE 333 Professor Yu(Kevin Cao April 1 2008 Objective The objective of lab

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