Lab 2 - EEE 333, ASU Spring 2008, Yu (Kevin) Cao Lab #2 Due...

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EEE 333, ASU Spring 2008, Yu (Kevin) Cao Lab #2 Due Thursday, March 6 th . The objective of this lab is to practice your VHDL coding and the modeling of combinational logic units. Submission : Demo your results to the TA at least one day before the deadline . Then place your VHDL files in the digital dropbox at myasu with the filename as: EEE333_Lab_2_your name. In addition, capture and paste the waveforms into the file. Convert the data to hexadecimal , rather than in binary, while taking the snapshot or showing the demo. Hand in a document with explanations of the tests and screen captures of the working tests and waveforms to the lab TA. For the screen captures, make sure the signals are on a white background. You can use the capture tool to alter it or alter it in modelsim. Put in figure captions explaining what the figures show. Put your name in the files themselves as comments at the top of each VHDL file and the top of the document that you hand in. Design of an 8-bit ALU
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