This preview shows page 1. Sign up to view the full content.
Unformatted text preview: EEE 333, ASU Spring 2008, Yu (Kevin) Cao Lab #3 Due Tuesday, April 1 st . The objective of this lab is to practice your VHDL coding, memory design, and test schemes. Submission : Demo your results to the TA at least one day before the deadline . Then place your VHDL files in the digital dropbox at myasu with the filename as: EEE333_Lab_3_your name. In addition, capture and paste the waveforms into the file. Hand in a document with explanations of the tests and screen captures of the working tests and waveforms to the lab TA. Put in figure captions explaining what the figures show. Put your name in the files themselves as comments at the top of each VHDL file and the top of the document that you hand in. Design and Test of SRAM Write the VHDL code for a 12-bit single port SRAM memory with 128 locations. Write a separate architecture as a state machine to test your design. It should write one of five patterns to the entire memory and then read the entire memory checking if the data is correct. Each pattern should be written memory and then read the entire memory checking if the data is correct....
View Full Document
- Spring '08