HW 2 - check your answers. 1. Data Types: Chapter 2 in...

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EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #2 Due Thursday, February 14th, 10am, submitted to me in class. The objective of this homework is to exercise your learning of VHDL syntax, basic module definitions and modeling of combinational logic. You can try to use modelsim to simulate and
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Unformatted text preview: check your answers. 1. Data Types: Chapter 2 in Ashenden’s book Exercises 1, 6, 7, 8 2. Composite Types: Chapter 4 in Ashenden’s book Exercise 4 3. Modeling Constructs: Chapter 5 in Ashenden’s book Exercises 3, 4...
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This note was uploaded on 09/29/2008 for the course ECE 333 taught by Professor Cao during the Spring '08 term at ASU.

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