HW 3 - solution

HW 3 - solution - if (IE2='1' or IE3='1') then...

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EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #3 1. VHDL Implementation library IEEE use IEEE_Std_logic_1164.all; entity FSM is port( clk,reset : in std_logic; F,IE2,IE3,PF : in std_logic; Stall : out std_logic; output : out std_logic_vector(2 downto 0)); end entity FSM; architecture behavior of FSM is type state is (F,E1,E2,E3,P); signal current_state:state; begin Moore:process(clk,reset) begin if reset='1' then current_state=F; elsif clk='1' and clk'event then case current_state is when F => output<="000"; if F='0' then stall <='1'; current_state <=F; else stall <='0'; current_state <=E1; end if; when E1 => output<="001"; stall <='0';
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Unformatted text preview: if (IE2='1' or IE3='1') then current_state &lt;=E2; elsif (IE2='0' and IE3='0') then current_state &lt;=F; end if; when E2 =&gt; output&lt;=&quot;111&quot;; if IE3='1' then current_state &lt;=E3; stall &lt;='0'; elsif PF='1' then current_state &lt;=P; stall &lt;='1'; elsif IE3='0' then current_state &lt;=F; stall &lt;='0'; end if; when E3 =&gt; output&lt;=&quot;101&quot;; if PF='1' then current_state &lt;=P; stall &lt;='1'; else current_state &lt;=F; stall &lt;='0'; end if; when P =&gt; output&lt;=&quot;100&quot;; if PF='1' then current_state &lt;=P; stall &lt;='1'; else current_state &lt;=F; stall &lt;='1'; end if; when others =&gt; NULL; END CASE; END PROCESS; END architecture behavior; 2. State Transition Diagram...
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This note was uploaded on 09/29/2008 for the course ECE 333 taught by Professor Cao during the Spring '08 term at ASU.

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HW 3 - solution - if (IE2='1' or IE3='1') then...

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