HW 3 - begin case CS is when redState =>...

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EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #3 Due Tuesday, March 18th, 10am, submitted to me in class. The objective of homework 03 is to practice the VHDL coding of finite state machines. Please review related lectures and book chapters to start. You may use modelsim to check your answers. 1. VHDL Implementation Write the VHDL codes to implement the following Moore type FSM: 2. State Transition Diagram Draw the state diagram of the following VHDL Moore type FSM, explicitly showing all don’t care conditions.
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library IEEE; use IEEE_STD_LOGIC_1164.all; entity FSM is port( clk, reset: in std_logic; red, green, blue: in std_logic; newColor: out std_logic); end entity FSM; architecture RTL of FSM is type Color is (redState, greenState, blueState, whiteState); signal CS, NS: Color; -- CS and NS must be signals to imply flip-flops begin FSM_COMB: process (red, green, blue, CS)
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Unformatted text preview: begin case CS is when redState => newColor <= 1; if (red = 1) then NS <= redState; else NS <= whiteState; end if ; when greenState => newColor <= 1; if (green = 1) then NS <= greenState; else NS <= whiteState; end if ; when blueState => newColor <= 1; if (blue = 1) then NS <= blueState; else NS <= whiteState; end if ; when whiteState => newColor <= 0; if (red = 1) then NS <= redState; elsif (green = 1) then NS <= greenState; elsif (blue = 1) then NS <= blueState; else NS <= whiteState; end if ; when others => newColor <= 0; NS <= whiteState; end case ; end process FSM_COMB; FSM_SEQ: process (clk, reset) begin if (reset = 0) then CS <= whiteState; elsif (rising_edge(clk)) then CS <= NS; end if ; end process FSM_SEQ; end architecture RTL;...
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HW 3 - begin case CS is when redState =>...

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