HW 4 - solution

HW 4 - solution - <='0'; data...

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EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #4 Data Path with Parity Check library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity parity is generic ( length : integer := 7); port ( clk : in std_logic; reset : in std_logic; r x : in std_logic; data_vd : out std_logic; data : out std_logic_vector(length-1 downto 0); p_error : out std_logic); end entity parity; architecture beh of parity is type state is (Start, C1, Parity_Rx); signal current_state: state; signal count:integer range length-1 to 0; signal parity :std_logic; begin Parity_cal : process (clk,reset) begin if reset='1' then
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Unformatted text preview: <='0'; data <=(others =>'0'); p_error <='0'; current_state <=Start; count <=0; elsif clk'event and clk='1' then case current_state is when Start => count <=0; if rx = '0' then current_state <= C1; end if ; when C1 => if rx= '0' then current_state <=Parity_Rx; else current_state <=Start; end if ; when Parity_Rx => if count=lenght-1 then current_state <=Start; data_vd <='0'; if parity = Rx then p_error <= '0'; else p_error <='1'; end if ; else count <= count +1; data_vd <='1'; data(count) <=Rx; end if ; when others => null ; end case ; end if ; end process Parity_cal; end architecture beh;...
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This note was uploaded on 09/29/2008 for the course ECE 333 taught by Professor Cao during the Spring '08 term at ASU.

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HW 4 - solution - <='0'; data...

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