Unformatted text preview: An example of the data stream is shown below: … 1 1 1 1 1 0 0 d6 d5 d4 d3 d2 d1 d0 parity 1 0 0 d6 d5 … When receiving the end character, the seven data bits should be transferred in parallel to the data output port. If there is a parity error, the output port ERROR should be asserted high (low if otherwise). Draw the registers and logic blocks as a schematic, as well as the controller state machine state diagram. Write the VHDL code to implement the controller state machine. Your codes should be parameterized, such that the machine is able to support 7-bit or 8-bit characters, based on the value in the input port LENGTH ....
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- Spring '08
- Parity bit, odd parity, 7-bit odd parity, controller state machine