HW 5 - solution

HW 5 solution - signal size integer:=length signal size1 integer:=length signal num_of_stage:integer:=0 signal xor_signal:std_logic_vector(length-1

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EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #5 Parity Tree Design library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity xor_out is generic ( length : integer := 8); port( rx : in std_logic_vector(length-1 downto 0); xor_output : out std_logic); end entity xor_out; --Architecture for First Question architecture beh of xor_out is signal xor_signal :std_logic_vector(length-1) ; begin xor_signal(0) <=rx(0); xor_output <=xor_signal(length-1); --Combitatorial logic to calculate the Xor of N-inputs Output_calc:For i in 1 to length-1 generate xor_signal(i)<=xor_signal(i-1) xor rx(i); end generate Output_calc; end architecture beh; --Architecture for Second Question architecture beh of xor_out is
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Unformatted text preview: signal size: integer:=length; signal size1: integer:=length; signal num_of_stage :integer:=0; signal xor_signal :std_logic_vector(length-1) ; begin --Sequential logic to confirm if the length is in power of 2 stage_calc:process(size1) begin while size1 !=0 loop assert size1 mod 2 !=0 report "Cannont be computed using Tree" severity error; size1 <= size1/2; num_of_stage <=num_of_stage+1; end loop; end process stage_calc; --Combitatorial logic to calculate the Xor of N-inputs xor_signal <=rx; xor_output <=xor_signal(0); stage_first:For j in 0 to num_of_stage-1 generate size<=size/2; stage:For i in 0 to size-1 generate xor_signal(i)<=xor_signal(2*i) xor xor_signal(2*i+1); end generate Output_calc; end generate stage_first; end architecture beh;...
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This note was uploaded on 09/29/2008 for the course ECE 333 taught by Professor Cao during the Spring '08 term at ASU.

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