Unformatted text preview: clock edge as shown in Fig. 1, where Q_next is the value of Q at the next cycle. What is the logic function to derive Q_next from T and Q? b. Define the state of this TFF as the value of Q. Draw the state diagram of a TFF. c. Fig. 2 shows a SetReset latch. Instead of a clock signal, the signals of set (S) and reset (R) control the value of Q. Note that S=R=1 is an illegal set of input, since Q and Q are not complementary under that condition. What is the logic function to derive Q_next from S, R, and Q? d. Define the state of an SR latch as the value of Q, and the control signal as the legal value of SR. Draw the state diagram of a SR latch....
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 Spring '08
 Cao
 Logic gate, sr latch, Boolean Logic DeMorgan, B+C A+ B+C

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