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Unformatted text preview: EEE 333, ASU Spring 2008, Yu (Kevin) Cao Homework #1 1. Boolean Logic ABC
000 001 010 011 100 101 110 111 2. (a) A+ B+C A+ B+C
0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 A
1 1 1 1 0 0 0 0 B
1 1 0 0 1 1 0 0 C
1 0 1 0 1 0 1 0 A B C
1 0 0 0 0 0 0 0 CMOS Implementation (A B + B ) B
= B (it is just a wire connecting the input and output. No gate needed) (b) A + A B C
= A + C = A C . Three NAND gates are needed. (c) A+ B +C A
= A, no gate needed. 3. Sequential Logic a. A toggle flipflop has the input T as an enable signal. This FF changes its state at the clock edge as shown in Fig. 1, where Q_next is the value of Q at the next cycle. What is the logic function to derive Q_next from T and Q? Q _ next = T Q + T Q
b. Define the state of this TFF as the value of Q. Draw the state diagram of a TFF. 1 0 0 1 1 0 c. Fig. 2 shows a SetReset latch. Instead of a clock signal, the signals of set (S) and reset (R) control the value of Q. Note that S=R=1 is an illegal set of input, since Q and Q are not complementary under that condition. What is the logic function to derive Q_next from S, R, and Q? Q _ next = S + R Q
d. Define the state of an SR latch as the value of Q, and the control signal as the legal value of SR. Draw the state diagram of a SR latch. 10 00, 01 0 01 1 00, 10 ...
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 Spring '08
 Cao
 Logic gate, sr latch, B+C A+ B+C

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