Midterm 02 - solution

Midterm 02 - solution - NAME: ; SID #: . EEE 333, ASU...

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NAME: ; SID #: . EEE 333: Spring 2008, Midterm – 02 1 EEE 333, ASU Spring 2008, Yu (Kevin) Cao Midterm – 02 March 27th, 9:15am-10:30am, PSA 118 NAME: , . SID #: . (LAST) (FIRST) Problem 1: (9) . Problem 2: (31) . Problem 3: (10) . Total (50) . Solution
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NAME: ; SID #: . EEE 333: Spring 2008, Midterm – 02 2 Problem 1: Process Statement (9 pts) The following codes define two processes for events occurring on the input ports: entity sig_assign is port (A, B, C, D : in bit; Y: out bit); end entity sig_assign; architecture behav of sig_assign is signal s1, s2 : bit; begin p1 : process (A, B, C) is begin s1 <= A and B and C; end process ; p2 : process (D, s1, s2) is begin Y <= not s2; s2 <= s1 and D; end process ; end architecture behav; a. Do these processes infer combinational or sequential circuit? Select the right answer. (3 pts) Ñ Combinational Ñ Sequential b. Assume an event occurs on “A” as shown below. Draw the timing graphs for other signals based on the concept of delta delay. Assume initially A=B=C=D=1, s1=s2=1, and Y=0. (6 pts) A s1 s2 Y X
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NAME: ; SID #: . EEE 333: Spring 2008, Midterm – 02 3 Problem 2: Finite State Machine (31 pts) The VHDL module below implements a finite state machine: entity flip is port ( A, B : in std_logic; X, Y : out std_logic;
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Midterm 02 - solution - NAME: ; SID #: . EEE 333, ASU...

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