cse331-week9(2)

cse331-week9(2) - CSE 331 Computer Organization and Design...

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CSE331 W09.1 KB Spring 2008PSU CSE 331 Computer Organization and Design Spring 2008 Week 9 Section 1&2Course material on ANGEL: cms.psu.edu [ Thanks to Mary Jane Irwin adapted from D. Patterson slides]
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CSE331 W09.2 KB Spring 2008PSU Head’s Up Last week’s material Number representation, basic arithmetic ops, MIPS ALU design This week’s material Designing a MIPS single cycle datapath - Reading assignment – PH 5.1-5.3, B.7 Next week’s material More on single cycle datapath design and exam review - Reading assignment – PH: 5.4, B.8, C.1-C.2 Reminders HW 6 is due March (by 11:55pm) Quiz 5 is due March (by 11:55pm) Exam #2 is March 6:30 to 7:45pm, 26 Hosler - People with conflicts should have sent email by now April - late-drop deadline
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CSE331 W09.3 KB Spring 2008PSU Datapath design tended to just work … Control paths are where the system complexity lives. Bugs spawned from control path design errors reside in the microcode flow, the finite-state machines, and all the special exceptions that inevitably spring up in a machine design like thistles in a flower garden. The Pentium Chronicles , Colwell, pg. 64
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CSE331 W09.4 KB Spring 2008PSU Review: Design Principles Simplicity favors regularity fixed size instructions – 32-bits only three instruction formats Good design demands good compromises three instruction formats Smaller is faster limited instruction set limited number of registers in register file limited number of addressing modes Make the common case fast arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands
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KB Spring 2008PSU We're ready to look at an implementation of the MIPS Simplified to contain only: memory-reference instructions: lw, sw arithmetic-logical instructions: add, addu, sub, subu, and, or, xor, nor, slt, sltu arithmetic-logical immediate instructions: addi, addiu, andi, ori, xori, slti, sltiu control flow instructions: beq, j Generic implementation: use the program counter (PC) to supply the instruction address and fetch the The Processor: Datapath & Control Fetch PC = PC+4 Decode Exec
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CSE331 W09.6 KB Spring 2008PSU Abstract Implementation View Two types of functional units: elements that operate on data values (combinational) elements that contain state (sequential) Single cycle operation Split memory ( Harvard ) model - one memory for instructions and one for data Address Instruction Instruction Memory Write Data Reg Addr Reg Addr Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data
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CSE331 W09.7 KB Spring 2008PSU Clocking Methodologies Clocking methodology defines when signals can be read and when they can be written falling (negative) edge rising (positive) edge clock cycle clock rate = 1/(clock cycle) e.g., 10 nsec clock cycle = 100 MHz clock rate 1 nsec clock cycle = 1 GHz clock rate State element design choices level sensitive latch master-slave and edge-triggered flipflops
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CSE331 W09.8 KB Spring 2008PSU State Elements
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cse331-week9(2) - CSE 331 Computer Organization and Design...

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