cse331-week10

cse331-week10 - CSE 331 Computer Organization and Design...

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CSE331 W10.1 KB Spring 2008 PSU CSE 331 Computer Organization and Design Spring 2007 Week 10 Section 1& 2 Section 2Course material on ANGEL: cms.psu.edu [ Thanks to Mary Jane Irwin adapted from D. Patterson slides ]
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CSE331 W10.2 KB Spring 2008 PSU Head’s Up Last week’s material Designing a MIPS single cycle datapath This week’s material More on single cycle datapath design and exam review - Reading assignment – PH: 5.4, B.8, C.1-C.2 Next week’s material Multicycle MIPS datapath implementation - Reading assignment – PH: 5.5, C.3
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CSE331 W10.3 KB Spring 2008 PSU Each MAS (microarchitectural specifications) included Pipeline and block diagrams Textual description of the theory of operation Unit inputs and outputs and protocols governing data transfers Corner cases of the design that were especially tricky New circuits required for implementation Notes on testing and validation The Pentium Chronicles , Colwell, pg. 82
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CSE331 W10.4 KB Spring 2008 PSU Review: Creating a Datapath from the Parts Assemble the datapath elements, add control lines as needed, and design the control path Fetch, decode and execute each instructions in one clock cycle – single cycle design no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., why we have a separate Instruction Memory and Data Memory) to share datapath elements between two different instruction classes need multiplexors at the input of the shared elements with control lines to do the selection Cycle time is determined by length of the longest path
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CSE331 W10.5 KB Spring 2008 PSU Review: A Simple MIPS Datapath Design Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU control RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 16 32 MemtoReg ALUSrc Read Address Instruction Instruction Memory Add PC 4 Shift left 2 Add PCSrc
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CSE331 W10.6 KB Spring 2008 PSU Adding the Control Selecting the operations to perform (ALU, Register File and Memory read/write) Controlling the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction I-Type: op rs rt address offset 31 25 20 15 0 R-type: 31 25 20 15 5 0 op rs rt rd funct shamt 10 Observations op field always in bits 31-26 addr of two registers to be read are always specified by the rs and rt fields (bits 25-21 and 20- 16) base register for lw and sw always in rs (bits 25-21) addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions offset for beq, lw, and sw always in bits 15-0
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CSE331 W10.7 KB Spring 2008 PSU (Almost) Complete Single Cycle Datapath Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr ALU ovf zero Data Memory Address Write Data Read Data MemWrite MemRead Register File Read Data 1 Read Data 2 RegWrite Sign Extend 16 32 MemtoReg ALUSrc Shift left 2 Add PCSrc 1 0 RegDst 0 1 1 0 1 0 ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11]
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cse331-week10 - CSE 331 Computer Organization and Design...

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