Homework_6 - Computer Science and Engineering 331 Computer...

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Computer Science and Engineering 331 Computer Organization and Design Spring 200 8 Homework #6 Design and Simulation of a 32-bit MIPS ALU Points: 25 (Pair Programming) Due: March 21 , 200 8, 11:55pm 1. Design and simulate the VHDL for the 32-bit MIPS ALU with overflow and zero detect depicted in W07&08.25 (slide 25 of week 7&8). The ALU should implement 10 R-type operations (shown in the table in W07&08.25). The first step is to follow the control lines and the functions shown in W07&08.39 to design a 4-bit ALU. Your VHDL description should be structural and constructed from 3 behavioral VHDL 1-bit ALU blocks, a special behavioral VHDL 1-bit ALU block for the most significant bit (also shown in W07&08.39) and a behavioral VHDL block for the zero detect logic. The next step is to construct the 32- bit ALU by wiring EIGHT 4-bit ALU blocks. The final overflow output of the 32-bit ALU is the overflow output from the most significant 4-bit ALU block. You also need a behavioral VHDL block for generating the final zero detection output. Your behavioral blocks should be
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This note was uploaded on 09/30/2008 for the course CMPEN 331 taught by Professor Bhat during the Spring '08 term at Pennsylvania State University, University Park.

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