cse331-week11_12 - CSE 331 Computer Organization and Design...

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CSE331 W11&12.1 KB Spring 2008 PSU CSE 331 Computer Organization and Design Spring 2008 Week 11&12 Section 1& 2 Kabekode V. Bhat: Course material on ANGEL: cms.psu.edu [ Thanks to Mary Jane Irwin adapted from D. Patterson slides]
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CSE331 W11&12.2 KB Spring 2008 PSU Head’s Up Last week’s material Designing a MIPS single cycle datapath This week’s material Multicycle MIPS datapath implementation, microprogramming - Reading assignment – PH: 5.5, 5.7, B.10, C.3-C.5 Next week’s material Input/Output – dealing with exceptions and interrupts - Reading assignment – PH: 5.6, 8.1, 8.5, A.7-A.8 CMPEN331 Exam #2: Wednesday, March 27, 2008, 6:30-7:45pm, 26 Hosler CMPEN331 FINAL EXAM Monday, May 5, 2008 10:10A-12:00P 112 BUCKHOUT (both sections 1 and 2)
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CSE331 W11&12.3 KB Spring 2008 PSU By the time it is externally visible that things have gone awry, many millions or even billions of clock cycles may have transpired. … as you stand there helpless and befuddled in the debug lab, the scales fall from your eyes, and you see clearly and ruefully that during design you should have provided an entire array of debug and monitoring facilities, with enough flexibility to cover all the internal facilities you wish you could observe right now. The Pentium Chronicles , Colwell, pg. 72
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CSE331 W11&12.4 KB Spring 2008 PSU Review: Single Cycle Data and Control Path Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 16 32 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Instr[31-26] Branch Shift left 2 0 1 Jump 28 Instr[25-0] 26 PC+4[31-28] 32
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CSE331 W11&12.5 KB Spring 2008 PSU Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instr especially problematic for more complex instructions like floating point multiply May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but It is simple and easy to understand Clk lw sw Waste Cycle 1 Cycle 2
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CSE331 W11&12.6 KB Spring 2008 PSU Multicycle Implementation Overview Each instruction step takes 1 clock cycle Therefore, an instruction takes more than 1 clock cycle to complete Not every instruction takes the same number of clock cycles to complete Multicycle implementations allow faster clock rates different instructions to take a different number of clock cycles functional units to be used more than once per instruction as long as they are used on different clock cycles, as a result - only need one memory - only need one ALU/adder
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CSE331 W11&12.7 KB Spring 2008 PSU The Multicycle Datapath – A High Level View Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout
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