cse331-week13 - CSE 331 Computer Organization and Design...

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CSE331 W13.1 KB Spring 2008PSU CSE 331 Computer Organization and Design Spring 2008 Week 13 Section 1&2 course material on ANGEL: cms.psu.edu [ Thanks to Mary Jane Irwin adapted from D. Patterson slides ]
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CSE331 W13.2 KB Spring 2008PSU Head’s Up Last week’s material Multicycle MIPS datapath implementation, microprogramming This week’s material Input/Output – dealing with exceptions and interrupts - Reading assignment – PH: 5.6, 8.1, 8.5, A.7-A.8 Next week’s material Intro to pipelined datapath design - Reading assignment – PH: 6.1 Final Exam: CSE 331 001 Monday, May 7, 2007 8:00A-9:50A 100 LIFE SCI CSE 331 002 Monday, May 7, 2007 8:00A-9:50A 100 LIFE SCI
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CSE331 W13.3 KB Spring 2008PSU Need new quote here The Pentium Chronicles , Colwell, pg. xx
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CSE331 W13.4 KB Spring 2008PSU Major Components of a Computer Processor Control Datapath Memory Devices Input Output Important metrics for an I/O system Performance Compatibility Expandability and diversity Dependability, flexibility, power needs, sensitivity Cost, size, weight
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CSE331 W13.5 KB Spring 2008PSU Input and Output Devices I/O devices are incredibly diverse with respect to Behavior – input, output or storage Partner – human or machine Data rate – the peak rate at which data can be transferred between the I/O device and the main memory or processor Device Behavior Partner Data rate (Mb/s) Keyboard input human 0.0001 Mouse input human 0.0038 Laser printer output human 3.2000 Graphics display output human 800.0000-8000.0000 Network/LAN input or output machine 100.0000-1000.0000 Magnetic disk storage machine 240.0000-2560.0000 8 orde rs of mag nitu de rang e
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CSE331 W13.6 KB Spring 2008PSU Communication of I/O Devices and Processor How the processor directs the I/O devices Special I/O instructions - Must specify both the device and the command Memory-mapped I/O - Portions of the high-order memory address space are assigned to each I/O device - Read and writes to those memory addresses are interpreted as commands to the I/O devices - Load/stores to the I/O address space done only by the OS How the I/O device communicates with the processor Polling – the processor periodically checks the status of an I/O device to determine its need for service - Processor is totally in control – but does all the work - Can waste a lot of processor time due to speed differences Interrupt-driven – the I/O device issues an interrupts to the processor to indicate that it needs attention
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CSE331 W13.7 KB Spring 2008PSU I/O in SPIM Processor Control Datapath Devices Receiver Transmitter SPIM supports one memory-mapped I/O device – a terminal with two independent units Receiver reads characters from the keyboard Transmitter writes characters to the display
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CSE331 W13.8 KB Spring 2008PSU Review: MIPS (spim) Memory Allocation Memory 2 30 words 0000 0000 f f f f f f f c User Code Reserved Static data Mem Map I/O 0040 0000 1000 0000 1000 8000 ( 1004 0000) 7f f e f f fc Stack Dynamic data $sp $gp PC Kernel Code & Data 8000 0080
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CSE331 W13.9 KB Spring 2008PSU Terminal Receiver (Input) Control with SPIM Terminal input is controlled via two memory- mapped device registers (i.e., each register
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This note was uploaded on 09/30/2008 for the course CMPEN 331 taught by Professor Bhat during the Spring '08 term at Pennsylvania State University, University Park.

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cse331-week13 - CSE 331 Computer Organization and Design...

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