Homework_7 - Computer Science and Engineering 331 Computer...

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Unformatted text preview: Computer Science and Engineering 331 Computer Organization and Design Spring 200 8 Homework #7 Points: 25 (Pair Programming) Due: Apr . 14 , 200 8 1. Using VHDL, build a processor that consists of a single cycle MIPS datapath and a control unit. It should support the execution of the MIPS instructions lw, sw, add, addi, sub, and, andi, or, ori, xor, nor, slt, slti, beq and j . The datapath is shown below. Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 16 32 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28 Zero Extend 16 1 Extend Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 16 32 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28 Zero Extend 16 1 Extend You can use the ALU (either your internal ALU control logic from HW#6 or the ALU control loci design in class (slide L10.13 will have to be modified) that you designed in HW#6. You will need to design the CSA logic for the various muxes using the same basic gate library as in HW#6. You can use process based code for the main control unit and the ALU control logic using a 20 ns and a 10ns control signal output delay, respectively. For generating the Clock signal, please refer to Section 4.6 in Yalamanchili. Zero/Sign Extend and Shift left 2 can be handled easily in the port map structural descriptions that interconnect components and thus incur no delay. You will be provided with the VHDL codes for the Register File, the Data Memory and a test Instruction Memory. Register File, the Data Memory and a test Instruction Memory....
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This note was uploaded on 09/30/2008 for the course CMPEN 331 taught by Professor Bhat during the Spring '08 term at Pennsylvania State University, University Park.

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Homework_7 - Computer Science and Engineering 331 Computer...

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