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Unformatted text preview: Place and Route for FPGAs 1 FPGA CAD Flow Circuit description (VHDL, schematic, ...) Synthesize to logic blocks Place logic blocks in FPGA Route connections between logic blocks FPGA programming file Physical design 2 Placement Goal: Determine which logic block within an FPGA should implement each of the logic blocks required by the circuit. Objective: Minimize the required wiring (wirelength driven placement). Balance the wiring density across the FPGA (routabilitydriven placement). Maximize circuit speed (timingdriven placement). 3 major classes of placers: mincut (partitioningbased) placers analytic placers simulated annealing based placers. 3 Simulated Annealing Simulated annealing (SA) mimics the annealing process used to gradually cool molten metal to produce a highquality crystal structure. SA takes an existing solution and then makes successive changes in a series of random moves. Each move is accepted or rejected based on an energy function . In order to escape from solutions which are local minima , it allows uphill moves that seemingly move to a less desirable solution. Probability of accepting an uphill move is controlled by the expression where is the resulting increase in the energy function and is the current tempera ture . The temperature is slowly decreased and the system finally comes to rest at a lowenergy configuration. 4 Simulated Annealing Based Placer An initial placement is created by assigning logic blocks of the circuit randomly to the available locations in the FPGA. A common cost function in wirelengthdriven placement is the sum over all nets of the halfperimeter of their bounding boxes. A move can be the exchange of locations of two randomly selected logic blocks. Initially, temperature is very high so almost all moves are accepted; it is gradually decreased as the placement is refined so that eventually the probability of accepting a move that makes the placement worst is very low. An advantage of simulated annealing based placer is the ease to add new opti mization objectives or constraints. But a drawback is the running time required. 5 Algorithm: Simulated Annealing Based Placer 1 begin 2 RandomPlacement(); 3 InitialTemperature(); 4 while (ExitCriterion() == False) do 5 while (InnerLoopCriterion() == False) do 6 GenerateViaMove(S); 7 ; 8 if then 9 if then with probability ; 10 end while ; 11 UpdateTemp(); 12 end while ; 13 return 14 end 6 MinCut Placement The given circuit is repeatedly partitioned into two subcircuits. Meanwhile, the chip area is partitioned alternately in the horizontal and vertical directions into subsections. Each subcircuit is assigned to a subsection. The process is repeated until each subcircuit consists of a single logic block and has a unique location on the chip area....
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 Fall '08
 Li

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