CSCE 3612 ch3-2

CSCE 3612 ch3-2 - CPUs Caches. Memory management. 2008...

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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. CPUs Caches. Memory management.
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Caches and CPUs CPU cache controller cache main memory data data address data address
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Cache operation Many main memory locations are mapped  onto one cache entry. May have caches for: instructions; data; data + instructions ( unified ). Memory access time is no longer  deterministic.
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Terms Cache hit : required location is in cache. Cache miss : required location is not in  cache. Working set : set of locations used by  program in a time interval.
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Types of misses Compulsory  ( cold ): location has never  been accessed. Capacity : working set is too large. Conflict : multiple locations in working set  map to same cache entry.
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Memory system performance h = cache hit rate. t cache  = cache access time, t mai n = main  memory access time. Average memory access time: t av  = ht cache  + (1-h)t main
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Multiple levels of cache CPU L1 cache L2 cache
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Overheads for Computers as Components 2 nd ed. Multi-level cache access time h 1  = cache hit rate. h 2  = rate for miss on L1, hit on L2. Average memory access time:
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This note was uploaded on 09/30/2008 for the course CSCE 3612 taught by Professor Goodrum during the Fall '08 term at North Texas.

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CSCE 3612 ch3-2 - CPUs Caches. Memory management. 2008...

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