CSCE 3612 ch4-1

CSCE 3612 ch4-1 - Bus-Based Computer Systems Busses. Memory...

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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Bus-Based Computer Systems Busses. Memory devices. I/O devices: serial links timers and counters keyboards displays analog I/O
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. The CPU bus Bus allows CPU, memory, devices to  communicate. Shared communication medium. A bus is: A set of wires. A communications protocol.
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Bus protocols Bus protocol determines how devices  communicate. Devices on the bus go through sequences  of states. Protocols are specified by state machines,  one state machine per actor in the protocol. May contain asynchronous logic behavior.
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Four-cycle handshake device 1 device 2 enq ack time device 1 device 2 1 2 3 4
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Four-cycle handshake, cont’d. 1. Device 1 raises enq. 2. Device 2 responds with ack. 3. Device 2 lowers ack once it has finished. 4. Device 1 lowers enq.
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Microprocessor busses Clock provides  synchronization. R/W is true when  reading (R/W’ is false  when reading). Address is a-bit bundle  of address lines. Data is n-bit bundle of  data lines. Data ready signals  when n-bit data is  ready. © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Timing diagrams
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© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.
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This note was uploaded on 09/30/2008 for the course CSCE 3612 taught by Professor Goodrum during the Fall '08 term at North Texas.

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CSCE 3612 ch4-1 - Bus-Based Computer Systems Busses. Memory...

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