CIC_design flow explanation

CIC_design flow explanation - CIC Referenced Flow for...

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CIC Referenced Flow for Cell-based IC Design 設計服務組 Version 1.0
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1 版本說明 版本編號 (Version) 日期 (Date) 說明 (Description) V. 1.0 2008/5/ 初版 Abstract CIC 整合了一個數位電路設計流程,並提供給學術界。本設計流程包含各階段的實 現及驗證的方法 , 驗證的目的是確保各個實現階段結果的正確性,項目包括有 function timing power DRC 等,越到實體階段所須驗證的項目就越多。 CIC 供的 Cell-Based Design Flow Logic Synthesis Place&Route Layout Merging 到最後 Tape out 的步驟。每個步驟階段都有對應的軟體,學生只要遵循此流程,配 CIC 提供的 Cell Library ,就可以完成電路晶片的實作。
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2 目錄 版本說明 .................................................................................................................................... 1 Abstract . ..................................................................................................................................... 1 目錄 ............................................................................................................................................ 2 1 The CIC Cell-Based Design Flow Overview. .................................................................... 3 2 The RTL Verification. ......................................................................................................... 4 2-1 RTL Code. .................................................................................................................... 4 2-2 RTL Simulation. ........................................................................................................... 6 2-3 Code Coverage Analysis. ............................................................................................. 7 3 Gate-level Pre-Layout Verification . ................................................................................... 8 3-1 To Generate Gate-level Netlist Using Logic Synthesis Tool . ...................................... 9 3-2 Gate-level Simulation . ............................................................................................... 10 3-3 Gate-level Power Analysis. ........................................................................................ 11 3-4 Formal Verification . ................................................................................................... 12 4 Gate-level Post-layout Verification . ................................................................................. 13 4-1 To Generate GDSII & Gate-level Netlist Using APR Tool. ....................................... 14 4-2 RC Extraction. ............................................................................................................ 15 4-3 Gate-level STA & Simulation . ................................................................................... 16 4-4 Gate-level Power Analysis. ........................................................................................ 16 4-5 Formal Verification . ................................................................................................... 17 4-6 DRC/LVS. .................................................................................................................. 18 5 Circuit-level Verification. ................................................................................................. 19 5-1 Replace True Layout. ................................................................................................. 19 5-2 DRC/LVS. .................................................................................................................. 20 5-3 Circuit Extraction. ...................................................................................................... 20 5-4 Circuit-level Simulation. ............................................................................................ 20 參考文獻 .................................................................................................................................. 21
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1 The CIC Cell-Based Design Flow Overview 對於數位電路設計, CIC 整合了一個基本的數位電路設計流程,並提供給學術界。 圖一所示, Cell-Based Design implementation 流程包含幾個主要的實現步驟: RTL coding Logic synthesis Place&Route Layout Merge ,在這些實現步驟當中還穿插各種 不同的驗證 , 驗證的目的是確保各個實現階段結果的正確性,項目包括有 function timing power DRC 等,越到實體階段所須驗證的項目就越多。 CIC 提供的 Cell-Based Design Flow Logic Synthesis Place&Route Layout Merging 到最後 Tape out 的步驟。 每個步驟階段都有對應的軟體,學生只要遵循此相關流程,配合 CIC 提供的 Cell Library ,就可以完成電路晶片的實作,提高學術界 IC 設計的水準。 RTL Code Logic synthesis RTL simulation Code coverage Analysis Gate-level Netlist Gate-level simulation Gate-level Power Analysis Formal verification Place&Route Gate-level Netlist DRC/LVS Layout Formal verification Gate-level simulation Gate-level Power Analysis Delay Caculation RC Extraction Layout Merging Layout Circuit Extraction DRC/LVS Circuit-level Netlist Circuit -level Simulation Tapeout RTL Verification Gate-level Pre-layout Verification Gate-level Post- layout Verification Circuit-level Verification Circuit -level STA Gate-level STA 圖一、 The CIC Cell-Based Design Flow
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4 2 The RTL Verification
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CIC_design flow explanation - CIC Referenced Flow for...

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