tutorial

tutorial - ViPS Group Tutorial Brian Lam July 2, 2003 1...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
ViPS Group Tutorial Brian Lam July 2, 2003 1 Introduction The purpose of this tutorial is to introduce tools that are commonly used in our research activities to new ViPS group members. The tutorial contains a set of exercises that can be used to familiarize the new group members with each of the tools. 2 Cadence Design Framework The Cadence Design Framework is an important tool in implementing a circuit in silicon. Layouts are drawn, checked for design rules, checked against schematics and extracted for simulation using this tool. This tutorial assumes basic layout knowledge from a course similary to ECE382: Digital Integrated Circuits. Tasks covered in this section Schematic entry Layout DRC LVS Extraction The first exercise involves the layout of a master and slave D flip flop as shown in Figure 1 and Figure 2. The purpose of this exercise is to go through the layout process from schematic entry to extraction. 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Figure 1: Transistor level schematic of a master slave DFF from Cadence. CLK CLK CLK CLK CLK Q D CLK CLK CLK CLK CLK Figure 2: Higher level schematic of a master slave DFF. 2
Background image of page 2
2.1 Starting Cadence and Schematic Entry 1. Start up Cadence by typing “icfb” in your cadence folder. You folder should be set up with the proper library files and technology files such as cds.lib. Consult the group’s Cadence Manager if you are having trouble. 2. Go to Library Manager and create a new library called “Tutorial”. Do not specify a path and Cadence will automatically create a folder called “Tutorial” within your Cadence folder. Choose “Attach to Existing Tech Library” and select the process which you will be using. Press OK and an empty library will be created. 3. Select the “Tutorial” library within Library Manager. Click on File–New–Cell View and a window will pop up. Change the cell name to “DFF” and select view name as “schematic” and click OK. 4. A new schematic has just been created. Draw your DFF using this tool. Consult the Cadence help pages for details on specific commands. From now on, if you would like to modify your layouts, you can access the schematic editor through the library manager but selecting the cell you want to edit from the appropriate library and double clicking on the schematic of the cell. Once you are done, click check and save and correct all your errors. For simplicity, keep all the transistors to minimum size allowed by the process technology. 2.2 Layout, DRC, LVS and Extraction 1. To design a layout, an initial floorplan should be made on paper. Once the floor plan has been done, drawing the layout is just a simple task. A sample layout for the DFF is shown in Figure 2. This particular layout constraints the design to only a single layer of metal. For this tutorial, you are encouraged to try your own design and can use up to two layers of metal for interconnection.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 10/01/2008 for the course ACMD 501 taught by Professor Nyquist during the Spring '97 term at USC.

Page1 / 10

tutorial - ViPS Group Tutorial Brian Lam July 2, 2003 1...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online