ENGRI1110_Lect7_08 - Tunneling-Switch Address Crossbar...

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Tunneling-Switch Tunneling-Switch Crossbar Circuits Crossbar Circuits US Patents 6128214, 6256767, 6314019 US Patents 6128214, 6256767, 6314019 Memory Switch Data lines Address lines 1 Abstraction of a Field-Programmable Gate Array
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Switchable Switchable Tunneling Resistor Tunneling Resistor Switch off "0" -10 -5 0 5 10 Current ( μ A) -2.0 -1.0 0.0 1.0 Voltage (V) Switch on "1" Read bit (measure resistance) Ti Pt Device = Molecule + Electrodes
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Communicate with the nanowires row selector (demux) memory grid selected column column selector (demux) selected row k-bit address selected memory cell k-bit address
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TUNNELING SWITCH LATCH: EXPT DATA D Data input Clock / control C1 C2 Q Data out SW1 SW2 E -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 Voltage (V) Input Output Trial 1 2 3 4 5 6 Signal restoration Inversion, if desired >100mV operating margin No amplification is needed because the device can reproduce the input signal adequately J. Appl. Phys. Feb 1, 2005
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Logical State Storage Signal Restoration Signal Inversion (Logical NOT)
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This note was uploaded on 10/01/2008 for the course ENGRI 1110 taught by Professor Giannelis during the Fall '07 term at Cornell University (Engineering School).

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ENGRI1110_Lect7_08 - Tunneling-Switch Address Crossbar...

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