CSE 281 CIS 341 Week 2

CSE 281 CIS 341 Week 2 - CSE 281/CIS 341 Chapter 2: IA-32...

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CSE 281/CIS 341 CSE 281/CIS 341 Chapter 2: IA-32 Processor Architecture
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2 Chapter Overview Chapter Overview General Concepts IA-32 Processor Architecture IA-32 Memory Management Components of an IA-32 Microcomputer Input-Output System
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3 General Concepts General Concepts Basic microcomputer design Instruction execution cycle Reading from memory How programs run
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4 Basic Microcomputer Design Basic Microcomputer Design clock synchronizes CPU operations control unit (CU) coordinates sequence of execution steps ALU performs arithmetic and bitwise processing
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5 Clock Clock synchronizes all CPU and BUS operations machine (clock) cycle measures time of a single operation clock is used to trigger events one cycle 1 0
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6 What's Next What's Next General Concepts IA-32 Processor Architecture IA-32 Memory Management Components of an IA-32 Microcomputer Input-Output System
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7 Instruction Execution Cycle Instruction Execution Cycle Fetch Decode Fetch operands Execute Store output
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8 Multi-Stage Pipeline Multi-Stage Pipeline Pipelining makes it possible for processor to execute instructions in parallel Instruction execution divided into discrete stages Example of a non- pipelined processor. Many wasted cycles.
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9 Pipelined Execution Pipelined Execution More efficient use of cycles, greater throughput of instructions: For k states and n instructions, the number of required cycles is: k + ( n – 1)
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10 Wasted Cycles (pipelined) Wasted Cycles (pipelined) When one of the stages requires two or more clock cycles, clock cycles are again wasted. For k states and n instructions, the number of required cycles is: k + (2 n – 1)
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11 Superscalar Superscalar A superscalar processor has multiple execution pipelines. In the following, note that Stage S4 has left and right pipelines (u and v). For k states and n instructions, the number of required cycles is: k + n
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12 Reading from Memory Reading from Memory Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are: address placed on address bus Read Line (RD) set low CPU waits one cycle for memory to respond Read Line (RD) goes to 1, indicating that the data is on the data bus Cycle 1 Cycle 2 Cycle 3 Cycle 4 Data Address CLK ADDR RD DATA
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13 Cache Memory Cache Memory High-speed expensive static RAM both inside and outside the CPU. Level-1 cache: inside the CPU Level-2 cache: outside the CPU Cache hit: when data to be read is already in cache memory Cache miss: when data to be read is not in cache memory.
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14 How a Program Runs How a Program Runs
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15 Multitasking Multitasking OS can run multiple programs at the same time. Multiple threads of execution within the same
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CSE 281 CIS 341 Week 2 - CSE 281/CIS 341 Chapter 2: IA-32...

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