CSE 281 CIS 341 Week 2

CSE 281 CIS 341 Week 2 - CSE 281/CIS 341 Chapter 2 IA-32...

Info icon This preview shows pages 1–16. Sign up to view the full content.

View Full Document Right Arrow Icon
CSE 281/CIS 341 CSE 281/CIS 341 Chapter 2: IA-32 Processor Architecture
Image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 Chapter Overview Chapter Overview General Concepts IA-32 Processor Architecture IA-32 Memory Management Components of an IA-32 Microcomputer Input-Output System
Image of page 2
3 General Concepts General Concepts Basic microcomputer design Instruction execution cycle Reading from memory How programs run
Image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
4 Basic Microcomputer Design Basic Microcomputer Design clock synchronizes CPU operations control unit (CU) coordinates sequence of execution steps ALU performs arithmetic and bitwise processing
Image of page 4
5 Clock Clock synchronizes all CPU and BUS operations machine (clock) cycle measures time of a single operation clock is used to trigger events one cycle 1 0
Image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
6 What's Next What's Next General Concepts IA-32 Processor Architecture IA-32 Memory Management Components of an IA-32 Microcomputer Input-Output System
Image of page 6
7 Instruction Execution Cycle Instruction Execution Cycle Fetch Decode Fetch operands Execute Store output
Image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
8 Multi-Stage Pipeline Multi-Stage Pipeline Pipelining makes it possible for processor to execute instructions in parallel Instruction execution divided into discrete stages Example of a non- pipelined processor. Many wasted cycles.
Image of page 8
9 Pipelined Execution Pipelined Execution More efficient use of cycles, greater throughput of instructions: For k states and n instructions, the number of required cycles is: k + ( n – 1)
Image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
10 Wasted Cycles (pipelined) Wasted Cycles (pipelined) When one of the stages requires two or more clock cycles, clock cycles are again wasted. For k states and n instructions, the number of required cycles is: k + (2 n – 1)
Image of page 10
11 Superscalar Superscalar A superscalar processor has multiple execution pipelines. In the following, note that Stage S4 has left and right pipelines (u and v). For k states and n instructions, the number of required cycles is: k + n
Image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
12 Reading from Memory Reading from Memory Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are: address placed on address bus Read Line (RD) set low CPU waits one cycle for memory to respond Read Line (RD) goes to 1, indicating that the data is on the data bus Cycle 1 Cycle 2 Cycle 3 Cycle 4 Data Address CLK ADDR RD DATA
Image of page 12
13 Cache Memory Cache Memory High-speed expensive static RAM both inside and outside the CPU. Level-1 cache: inside the CPU Level-2 cache: outside the CPU Cache hit: when data to be read is already in cache memory Cache miss: when data to be read is not in cache memory.
Image of page 13

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
14 How a Program Runs How a Program Runs
Image of page 14
15 Multitasking Multitasking OS can run multiple programs at the same time.
Image of page 15

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 16
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern