ECE 475 –Lab Two MIPS R3000 Pipelined Processor Objective You should convert your multi-cycle MIPS Verilog model from the previous lab into a pipelined MIPS model with full bypassing and a single branch delay slot. We expect this lab to be more challenging than the previous labs, so please start early. Remember to submit your lab electronically once you are finished. We highly recommend you draw a “paper and pencil” block diagram showing the datapath of your pipelined processor (including the bypasses and the branch delay slot). The block diagram should include all pipeline registers, multiplexers, and major datapath elements, and should be labeled with the signal names from your Verilog model. Use vertical lines to divide the five pipeline stages and dashed vertical lines to show phases (half stages) where necessary. This lab is not split into multiple parts; the entire lab will be graded out of 100 points. Lab Setup Delete all large files from the previous lab that you do not absolutely need anymore. Then you have two options: a)Use your Lab One submission as the starting point. Copy your lab1folder into lab2, then unzip Lab Two’s testfolder cd ~ ; mkdir ece475/lab2cp ece475/lab1/* ece475/lab2/ unzip /classes/ece475/labs/lab2test.zip Bewarethat any bugs you haven’t caught in lab1 will continue to cause you trouble if you choose this route. On-ly if you are absolutely sure your processor works 100% should you use it. For that reason, we recommend the next option. b)Start from a working non-pipelined R3000 that we provide (highly recommended, for your and our conveni-ence). To do so, from your home folder, unzip /classes/ece475/labs/lab2.zipas you did in earlier labs. The testfolder is included. First Steps Now you are ready to begin pipelining your processor. We have broken down the Verilog changes into two parts. The parts described below should all be done before you begin to add the bypassing logic. The following change in rf.vneed only be made if you want to run samplebefore you add bypassing: // Special handling for syscall instructions: initial begin // Initializes register r0 with zeros RAM = 32’b0;RAM = 32’b0;// new code RAM = 32’b0;// new code RAM = 32’b0;// new code end After you implement bypassing, you should remove the new code, as it will no longer be needed. Eliminating the State Register The current processor model is non-pipelined. As a result, there is a state register called Statethat changes its value with the processor’s clock, enabling the IF, RD, EX, MEM, and WBstages sequentially.
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