HW2 - HOMEWORK #2 ECE 4750/CS 4420 Computer Architecture...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
HOMEWORK #2 ECE 4750/CS 4420 – Computer Architecture Due Friday, October 10 th at midnight Problem 2.1 Advanced Memory Hierarchy [25 points] You are trying to determine what sort of cache structure to use for this 8-bit computer. There are two kinds of cache designs to consider. Cache D is a direct-mapped cache with 4 lines with 16 bytes/line. Cache F is fully associative, using a least recently used replacement policy, with 4 lines with 16 bytes/line. Addresses are 12 bits long and are byte addresses. On a hit, the access takes 1 cycle. On a miss, it takes 20 cycles. (a) In the following chart, mark the part of the address used for the tag, the line index, and the offset within the line. 11 10 9 8 7 6 5 4 3 2 1 0 Cache D: Cache F: (b) You are testing the cache by accessing the following sequence of hexadecimal byte addresses, starting with empty caches. Complete the following tables for both Cache D and F showing the progression of cache contents as accesses occur (in the tables, ‘inv’ = invalid, and the column of a particular cache line contains the {tag,index} contents of that line; e.g. for the address ‘110,’ L1 gets the value ‘11’). You only need to fill in elements in the table when a value changes. Cache D Address Part b) Part c) line in cache hit? line VC hit? L0 L1 L2 L3 VC 0x110 inv 11 inv inv no inv no 0x101 10 0x123 12 0x201 20 10 0x15C 0x102 0x136 0x202 0x137 0x124 0x103 0x15D 0x203 Cache D Cache D with Victim Cache Total Misses Total Cycles
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Cache F Address Part b) Part c) line in cache hit? line VC hit? L0 L1 L2 L3 VC 0x110 11 inv inv inv no inv no 0x101 10 0x123 12 0x201 20 0x15C 0x102 0x136 0x202 0x137 0x124 0x103 0x15D 0x203 Cache F Cache F with Victim Cache Total Misses Total Cycles (c) In order to improve performance, you have decided to add a victim cache. This will be one
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 5

HW2 - HOMEWORK #2 ECE 4750/CS 4420 Computer Architecture...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online