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Lab_One_08_09 - ECE 475 Lab One MIPS R3000 Non-pipelined...

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ECE 475 Lab One MIPS R3000 Non-pipelined Processor Objective You will be given a Verilog model of a non-pipelined MIPS R3000 microprocessor with some bugs and a few missing instructions. You will be asked to fix the problems and to add the missing instructions. Remember to submit your project electronically once you are finished. Model Description The Verilog model is able to execute real MIPS code generated by our MIPS gcc cross-compiler, including emulation of all syscall (operating system call) instructions. The Verilog code is broken down into ten files with the top-level file called mips.v . The mips.v file handles the interface between the processor and the memory system (loads and stores) and instan- tiates cpu.v . cpu.v in turn instantiates the various processor components, which roughly follow the five stages of the execution of a MIPS instruction: Instruction Fetch (IF), Register Decode (RD), Execution (EX), Memory (MEM), and Writeback (WB). Lab Setup Expand /classes/ece475/labs/lab1.zip the same way you did in Lab Zero. All the files needed for Lab One will be in the folder ece475/lab1/ . Your work should be done in this folder. The lab will be graded out of 100 points: 25 points for Part 1, 30 points for Part 2, and 45 points for Part 3. Running Your First MIPS Program In the folder ~/ece475/lab1/test/ type: gmake This will compile and cross-assemble some C files inside the test subfolder. You only need to do this once, or after mak- ing changes to the C files. In the folder ~/ece475/lab1/ type : ncverilog *.v +access+r +nc64bit This will compile your Verilog files and start the simulator. Once you are asked for a file name, enter test/hello . The simulator is fairly fast, but be patient when running larger C programs or when there are many people using the same machine. In the folder ~/ece475/lab1/test/ you will find a file called Makefile . Take a look at this file using a text editor. When you write a new C or assembly code program of your own, the IMAGES= line of this file must be modified for gmake to work. If the assembler generates error mes sages while handling a “.s” file , it is likely that there are trailing spaces after at the end of a line. Delete these and try again. The simulator for ECE 475 has a very useful command called $disasm . The $disasm command takes as input a 32-bit signal that represents an instruction and displays on the standard output the corresponding MIPS assembly code. Go to the always block around line 75 in the mips.v file and uncomment the $disasm statement. Execute the test/hello program again as described above. To view the output one page at a time, run ncverilog *.v +access+r +nc64bit | more . You can also pipe the entire output into a file by running ncverilog *.v +access+r +nc64bit > filename . However, for
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either of these options, you may have to blindly type the program name since you will not see the prompt. The output of the simulation is also written to the file ncverilog.log.
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