L5.Caches_I_6pp - Announcement HW1 will be out tomorrow...

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1 ECE4750/CS4420 Computer Architecture L5: Memory Hierarchy Basics Edward Suh C omputer S ystems L aboratory suh@csl.cornell.edu 2 Announcement HW1 will be out tomorrow Individual assignment Reading: Appendix C.1-3 ECE4750/CS4420 — Computer Architecture, Fal 2008 3 Overview Memory hierarchy basics memory technologies principle of locality Caches concepts: block, write policy, associativity, block replacement performance estimation: average memory access time ECE4750/CS4420 — Computer Architecture, Fal 2008 4 The Memory Wall ECE4750/CS4420 — Computer Architecture, Fal 2008 Time μProc 60%/year DRAM 7%/year 1 10 100 1000 1980 1981 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 DRAM CPU 1982 Processor-Memory Performance Gap: (grows 50% / year) Performance [From David Patterson, UC Berkeley] 5 Research Efforts ECE4750/CS4420 — Computer Architecture, Fal 2008 % of ISCA papers dealing principaly with caches 0 5 10 15 20 25 30 35 6 Industry ECE4750/CS4420 — Computer Architecture, Fal 2008
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2 7 On Memory Hierarchy “Ideally one would desire an indefinitely large memory capacity such that any particular […] word would be immediately available […] We are […] forced to recognize the possibility of constructing a hierarchy of memories , each of which has greater capacity than the preceding but which is less quickly accessible.” Burks, Goldstine, and von Neumann , 1946 ECE4750/CS4420 — Computer Architecture, Fal 2008 8 Typical Memory Reference Patterns ECE4750/CS4420 — Computer Architecture, Fal 2008 Address Time Instruction fetches Stack accesses Data accesses 9
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L5.Caches_I_6pp - Announcement HW1 will be out tomorrow...

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