This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: TL/F/5943 CD4007M/CD4007CDualComplementaryPairPlusInverter February 1988 CD4007M/CD4007C Dual Complementary Pair Plus Inverter General Description The CD4007M/CD4007C consists of three complementary pairs of N- and P-channel enhancement mode MOS transis- tors suitable for series/shunt applications. All inputs are pro- tected from static discharge by diode clamps to V DD and V SS . For proper operation the voltages at all pins must be con- strained to be between V SS b 0.3V and V DD a 0.3V at all times. Features Y Wide supply voltage range 3.0V to 15V Y High noise immunity 0.45 V CC (typ.) Connection Diagram Dual-In-Line Package TL/F/5943–1 Top View Note: All P-channel substrates are connected to V DD and all N-channel substrates are connected to V SS . Order Number CD4007 C 1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A. Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin V SS b 0.3V to V DD a 0.3V Operating Temperature Range CD4007M b 55 § C to a 125 § C CD4007C b 40 § C to a 85 § C Storage Temperature Range b 65 § C to a 150 § C Power Dissipation (P D ) Dual-In-Line 700 mW Small Outline 500 mW Operating V DD Range V SS a 3.0V to V SS a 15V Lead Temperature (Soldering, 10 seconds) 260 § C DC Electrical Characteristics CD4007M Limits Symbol Parameter Conditions b 55 § C a 25 § C a 125 § C Units Min Typ Max Min Typ Max Min Typ Max I L Quiescent Device...
View Full Document
This note was uploaded on 10/19/2008 for the course ECE 2B taught by Professor York during the Winter '07 term at UCSB.
- Winter '07