ece475-lec02 - Announcements Available on...

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ECE 475/CS 416 Computer Architecture Prof. Jos é F. Mart í nez C omputer S ystems L aboratory [email protected] ECE 475/CS 416 — Computer Architecture, Fall 2005 Prof. Martínez Announcements ! Available on CMS ( ) Homework 1 Lab 0–2 handouts ! Available on ECE Linux systems: Lab 0–1 Verilog code ! In-class Q&A dynamics Cost and Performance ECE 475/CS 416 — Computer Architecture, Fall 2005 Prof. Martínez The Design Process Estimate Cost & Performance Bad Ideas Mediocre Ideas Good Ideas ECE 475/CS 416 — Computer Architecture, Fall 2005 Prof. Martínez Estimating IC Cost C IC = C die + C d - test + C pkg + C p - test Y C die = C wafer N die Y die ECE 475/CS 416 — Computer Architecture, Fall 2005 Prof. Martínez Dies per Wafer (Why not square wafers ?) N die = A w A d - L w 2 L d = π r 2 A d - 2 π r 2 A d
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ECE 475/CS 416 — Computer Architecture, Fall 2005 Prof. Martínez Die Yield ! Y wafer Wafer yield (assume 1.0); 1- Y wafer is fraction of useless wafers ! D – Defects per unit area (typ. 0.4 to 0.8) ! ! inversely proportional to number of masking levels (typ. 4.0) ! Manufacturing dictates most variables ! Architect can control A die : transistor count! Die cost proportional to A die 4 ! Need good return on additional transistors Y die = Y wafer 1 + D A die α - α ECE 475/CS 416 — Computer Architecture, Fall 2005 Prof. Martínez Cost Trends: Time, Volume 1MB in 1977: $5,000; in 1995: $10; in 2000: 35¢ ECE 475/CS 416 — Computer Architecture, Fall 2005 Prof. Martínez Cost is Not Price! ECE 475/CS 416 — Computer Architecture, Fall 2005 Prof. Martínez The Design Process Estimate Cost & Performance Bad Ideas Mediocre Ideas Good Ideas ECE 475/CS 416 — Computer Architecture, Fall 2005 Prof. Martínez Estimating Performance !
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