This preview shows pages 1–10. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview:  6.1  Chapter 6 Problem Solutions 6.1. 6.2. (Note: Propagation delays are assumed to be zero.) 6.2  6.3. (Note: Propagation delays are assumed to be zero.) 6.4. (Note: Propagation delays are assumed to be zero.) 6.3  6.5. (Note: Propagation delays are assumed to be zero.) 6.6. (Note: Propagation delays are assumed to be zero.) 6.4  6.7. (Note: Propagation delays are assumed to be zero.) 6.8. (Note: Propagation delays are assumed to be zero.) 6.5  6.9. (Note: Propagation delays are assumed to be zero.) 6.10. The proposed network encounters difficulties when J=K=1 and C=1 for a long period of time. As a result of the feedback lines, the network toggles. After the propagation delays through the network, the toggling action again occurs. This toggling action continues as long as C=1. That is, the network oscillates at a frequency determined by the propagation delays through the network. To avoid this problem, the time in which C=1 must be controlled so that it does not exceed the propagation delays of the network. In addition, delays at the output terminals may be necessary since minimum pulse width requirements of the latch must be met. 6.6  6.11. (Note: Propagation delays are assumed to be zero.) 6.12. (Note: Propagation delays are assumed to be zero.) 6.7  6.13. (Note: Propagation delays are assumed to be zero.) 6.14. (Note: Propagation delays are assumed to be zero.) 6.8  6.15. (Note: Propagation delays are assumed to be zero.) 6.16. (a) Referring to Fig. 6.21a, when PR __ =1 and CLR ___ =0 the output of gate 6 is forced to 1 and the output of gate 5 is forced to 0. Hence, the flipflop resets. When CLR ___ =0, changes in D are not observed since gate 4 output is held at 1 by CLR ___ . Similarly, changes in C do not affect the output of gate 2. Finally, even though the output of gate 3 changes with changes in C, the output of gate 6 is held at 1 by CLR ___ . Therefore, the behavior of the flipflop is independent of the behavior on the C and D lines when PR __ =1 and CLR ___ =0. (b) When PR __ =0, the output of gate 5 is forced to 1. The output of gate 2 changes with changes in C, but cannot affect the output of gate 5 since its upper input is 0. The upper two inputs to gate 3 are always opposite. Therefore, a 0 input appears at gate 3, causing its output to be always 1. With all three inputs to gate 6 at 1, its output is held at 0. Thus, the flipflop sets. Changes in D are blocked at gate 3 since one of its upper inputs is always 0. 6.9  6.17. The master follows the D input as long as the clock is low. 6....
View
Full
Document
This note was uploaded on 10/26/2008 for the course ENEE 244 taught by Professor Petrov during the Spring '08 term at Maryland.
 Spring '08
 PETROV

Click to edit the document details