lecture13

lecture13 - Foundations of Embedded Systems A Term Fall...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Foundations of Embedded Systems A Term Fall 2008 Lecture #13: Using the ADC12 Analog-to-Digital Converter-Reading for Today: 430 User's Manual Ch 20 Reading for Next Class: ADXL330 Datasheet HW #4 (on web): Due FRIDAY 9/26/2008 Lab #2 (on web): Due Tuesday 9/30/2008 Exam #2 Now Tuesday 9/30/2008 4pm Last Class : >> Introduction to Analog-to-Digital Conversion >> Mapping output of analog sensors to an ADC (FSR, Resolution, Dynamic Range) MSP430F449 Analog-to-Digital Converter (ADC12) 8 channel, 12-bit sample and hold ADC (200k samples per second max.) Analog inputs A0-A7 available on AEXT header Configure are use by setting values in various control registers ADC12 Control and Data Registers (MSP430 Users Guide Ch 20) >> ADC12 conversion core configured using ADC12CTL0 and ADC12CTL1. ADC12CTL0 controls the following options-- Sample and Hold time (SHT1x and SHT0x)-- Multiple sample conversion method (MSC)-- Reference Voltages (REF_25 and REF_ON)-- ADC12ON bi t -- Enable and start conversion (ENC and ADC12SC)-- Overflow/Conversion time interrupt enables (ADC120VIE, ADC12TVIE) ADC12CTL1 controls the following options-- Conversion start address (CSTART ADDx)-- Sample and hold source select (SHSx)-- Sample and Hold pulse mode selectable (SHP)-- Invert signal sample and hold (ISSH)-- ADC12 clock divider (ADC12DIVx)-- ADC12 clock source select(ADCSSELx)-- Conversion mode select (CONSEQx)-- ADC12 busy/conversion not complete bit (ADC12BSY) >> Results from each channel are stored in the low 12 bits of one of 16 Conversion Memory Registers (ADC12MEMx) >> Each memory register has a corresponding Conversion Memory Control Register (ADC12MCTLx) Each ADC12MCTLx controls the following options for its Memory Register-- End of Sequence (EOS) = Is this channel the end on a sequence of channels that are to be converted-- Select Reference Voltages (SREFx) = -- Analog input channel selection (INCHx) = So what does the programmer need to do to use ADC12? 1) Select ADC Core Behavior : In ADC12CTL0 and ADC12CTL1 registers -- Clock source and divider-- Sample and hold behavior-- Reference Voltages 2) Select Conversion Mode required: CONSEQx bits in ADC12CTL1 register-- Single channel or a sequence of channels-- Also single conversion or repeated conversions 3) Select input channel(s)...
View Full Document

Page1 / 8

lecture13 - Foundations of Embedded Systems A Term Fall...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online