lect18_notes

lect18_notes - Foundations of Embedded Systems A Term Fall...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 4
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 6
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 8
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Foundations of Embedded Systems A Term Fall 2008 Lecture #18: Under the Hood--Introduction to MSP430 Assembly Language Reading for Today: User's Guide Ch 3.3 Reading for Next Class: User's Guide Ch 3.4 Lab #3 (on web) : Report due 10/7/2008 HW #5 (on web): Due 10/9/2008 The MSP430 doesn't actually speak C.... >> C is a_higher level language — Useful to human programmers to efficiently capture logic flow, arithmetic operations, etc. Program development steps in a typical development environment.... Edit, Compile, Link, Load, Execute \ Machine. Co A: (inns-trading fif— -> Execute what? What is actually stored in “Code Memory” :2) M U Mbers H-..“ Consider this simple C program void main( ) { int a,b,c; WDTCTL' = WDTPW + WDTHOLD; // Stop watchdog timer a = 1002; b == 47; c == a+b; Let's look at it in IAR Kickstart Microprocessors only understand their MACHINE CODE. >> Machine codes are binary codes that specify operations and operand iii 0p 5:43 In each field depencls on PfDCessor- anti ‘ he Lnslrudion [OPCODE source code data size codes destination code I In MSP 430 Instructions can be 2—6 bytes long ;:>MD$'_T Rxsc ’ProceSSorS have i:\xei lame“th 'mSn‘wcl‘tans 2) Longew er LAS‘i'erJCXl’lOeA ‘er [Oi/\‘Jé‘r E+ +¢ch *0 Saith =>l Bus castle or 3bus LLg/C/Cfi/O.‘ In C we can write a=a+b; (Or, a+=b;) A rough machine code translation — of the addition only -- might be t l \ >> 0101D111p000fl000 = ADD the word in R7 to the word in R8 and t g i leave the result in R8 5 » S‘zeColCQWDVA Oiot : OPCODE. {Ear ADD (Dc/DO.— Daca. i OiH 1 Sac. opened» em ‘000 I DEEP 0‘35rw'db =>R$ >> Assembly Instructions are mnemonics mapped 1 to 1 with a processor 's opcodes ADD R7, R8 ; R8 = R7 + R8 OPCDDE grow» 4: 0 >> MSP430 instruction set has only 27 base opcodes (Car-e I n 5 ‘l( U C24 0‘4 5) ::> EOJJA has Qn‘ui/UQ Texas Ins‘lvumem‘lS SpecZCt‘cé OPCODES wudt ska CPU can AeCoJQ. >> TI documents an additional 24 emulated instructions " Don \ )‘c hCLV fl 3 e Pcurccie 'x' v k OPCODE s K {\ij \Vb) > +€flcl~€A +0 mavk e ea 3 Te, k $0 0r LOO"th v / ‘ ‘ ~_ _( \x\ V / =2 ASSemb/e/ Quit) anode? unlit/J replaces w ULK fftuwakrfi \. ’—/ r» n m .’ J‘ m c «Ln/l l r in”. ; This is an example of an MSP430 assembly program NAME PUBLIC EXTERN EXTERN ORG DW RSEG main MOV MOV MOV CALL ‘0 ‘I CALL MOV CALL done_it JMP main ; Name of program module main ; make the main function visible 1_shift ; import a; function r_shift ; import another function OFFFEh ; Set RESET vector: addr. of main main CODE ; define relocatable code segment #0x400,SP ; define address of Stack ; Stack size set in Proj Opt #0ABCDh,R4 // R4 = OxABCD ' #4h,R5 // R5 = 4 #r_shift ; Call external r_shift funct. Can call a function within same named module without declaring as EXTERN #messR4 ; Call local messR4 function #4,R5 ; R5 = 4 #l_shift ; Call external r_shift funct. done_it ; loop forever on this line ; This is another functions inside same module ; It serves no useful purpose (just messes up R4) ADD SUB RET messR4 END #120,R4 #22,R4 main ; end of program module main An assembler program will contain... 2ft Qmu‘CCi ‘3' L ‘Ln swiruci‘iom 5] 3 l in sin; 0+ lav" B 1) Assembly Instructions ~ A 2'7 C 0 re £0? NUDV #4“: Rg 3R3: OXOOOL‘ CALL, fl»r..5ki{‘{,. // can Hm Qumfim n sing ~ \ a, 4 7 \ 4, ,er‘tbn 1C0." credm‘g 2) Assembler Directives 1 [)5 C“ +” 0‘5 Ln 5 H, ‘ / _ a o ra m, 0k woriklncs (L$bem\3\\3 9” Cd 7—) GSSemkitj Earecri‘wes usté +0 COH‘CKESU(Q ‘H‘Q “N, , .__.—-"‘\_‘_"_ -’l_,,i.AA\~--MWWNMWNI m I, 7 Q ‘ic. . T x Tan D g 5 G) D S 3) Comments ’ - 3 54—}‘filfls o 1?- Com m evx‘i-S 5 giutméajé aésemmfi Cammeen‘lj // C 543%:79. Commewi-s are (Di/<- M [2.511% \Cou’ muii‘R \x‘ne Commen‘i '3 3U Software Architecture of a Microprocessor >> What you must know about a microprocessor in order to program it 1. CPURegisters — 16 sixteen bit registers 9 Tempo (mfg SJTOWUQQ Lfi$lée CPU R0 = Program Counter R1 = Stack Pointer Ta (1944“ f) “016$ AAéress OJ? NEXT £ns+m+wn :> Hows (Léévc‘ss ‘0! ‘VM’ 9 ksmgk => I“Cremevfieé Auwmmfi CALLy 105 C Y’U ésiaok as a (Nag) WW" 5 5cm ; i .\ *3 a) DOM‘T mess (OHM we T’Cl => Don Jr megs Led-k 3‘ R2 = Status Register (status flags) R3 = Constant generation A S 4 Ma) , , ~ 1 Con . c,- ‘ , i e 1 $ “Fxx @ => WC W4 e» t“ irrisgtmm -=> W W . r 3 R4 — R15 are User Registers {LN 9 pg: ~C ‘6 'A ~.> Am lame *0 warm er 5 3 - ( s: \o ~ 4 3 10¢ (p4 k 0 fl 3 2. Memory model [13$ “A (DC? W‘eW‘O “r ‘3 5> $126: a? wen/A : No 10113 3? 1L\VV\OL)1\‘\‘ 0‘? RAM 3; 1 sh: (55KB 67 {lmoumi U"? Fla _ _\. noon __ Cage m emoflg QKQ SPQCR‘CRQA ((63 A€$+ MAO ——¥—— ;> MS“? \/\0\5 '7 3:10 6L5” aélvees morsz 4. Instruction set >3 f thong-oz O?CODES ‘chg,+ Jc/kQ : é: o: a. CWJ reCO‘b "“ 2 e 5 Address Modes = The ways the src and dest operands are specified >> MSP43O support 7address modes for src operands and 6 for dest 7 >> See lect18.s43 fOZ/iodeéximpl: qr {U A 4H} S C 0C] 6 for (6 $3 | i 'r ‘4‘ r) fi ‘ ' r RegiStel‘ M0d§= Both src and dest operands are CPU registers m Ode e} (“k “l ‘P MOV R14,R15 // Cop p3 42kg ward an R1 ta R 15’ // (7m Risa : Rum Le+ leLl:OFFOl/\ MA kvfi’, S‘H 5AM .\ N , . N9“) R‘W‘ OPPOH CLAA ‘R\€:OFFOL\ T105 (XC\/(£(€$Skr\3 m Ocl e i 3 PA $7 Foix C PU _ 9 (id-Ola a ’I’CQALJ Ln s EAe C PU >> Suffix .B (like MOV.B) means operation is on a BYTE >> Suffix .W (like ADD.W) or it; suffix means operation is on a WORD I l Immediate Mode Assigns fixed value to CPU register or memory location M / ADD #5,R15 Elihu S” J‘ro Rw’ (.1115: Rt? +§> ‘2 lYXOv‘ 7 w \ x . , fiOxSFJ l'UU COPYS Kkke BVT: 3ph to 41kg / l/ ‘ <( O! ) \chflk on Ln MEYWZMIQ lcklo-Glécl F00 (A V‘/ \./\\/ w / WV» \_\ . . . . LC'/fl\x§ 33 Q sac; onllé aAerSfima ‘”""'\aw/ NW“ cw\‘+ reéLQC‘xvxe \Hme value ) a; |O&\l[ n ero B FED // Ema laied iné‘frua‘l‘i 0 // max/-3 41:0,]:00 Indexed Mode n(Rx) = Adds offset n to contents of RX to form the memory address of the operand ; Assume R4 = 334h and the word stored at memory location 2334b is 8765 MOV #0x2000(R4), R15 ; R15 = 8765 decimal ill/H‘s &C£K£LV€5S Wtcdéi CCUA be“ 0561‘ +0 LMPIQWQA4 \OOvUL/‘p “tablesj cw’ Okrt’éufj“) Symbolic Mode: Accessing a memory location using its label MOV R15, FOO ; copy the contents of R15 to memory location labeled FOO ’/ RM: RM + +he word aircraé cal VV\€VY\DrL/3 ((CHOA B16411 AD D BAR) Rm Absolute Mode = Accessing a memory location using its label as an address MOV R15, &FOO ; copy the contents of R15to memory location at the address ; labeled FOO // :R\L\ + Can-lQA-l3 Og Memol‘td ADD QBAR) RM A Nata/kg agglolress lathe/lei 314:2 ***Symbolic Mode and Absolute Mode are equivalent for labels defined within the same program file (or module) \ ’1 @Prolxrblcj more *0 U58 &b$0lUl€ Mcdfflgdw‘ben goo UJccvan +rl\€ FA“ +am—lg x11: A ICC/L‘l’ldfl \ ("\‘Cj c“: (‘0 U 5 MACM I'Jrl/l Indirect Mode: Accessing memory location whose address is stored in a CPU register ** Most powerful address mode because address of data is totally under program control. Address operands are not hard-coded! ; Assume a double (32—bit) word 01005A5Ah is stored beginning at address 0202b ‘ ; The address 0202h is labeled dbl_X / lord d V95 5 L, 0% label—“Mm #JZa‘beiJ-mmnelj MOV fidbLX, R12 ; R12 = 0202h MOV @R12, R10 ;R10 = 5A5Ah ; Now I can update the values of R12 and access another memory location INCD R12 ; increment R12 by 2, R12 = 0204h MOV @R12,R11 ;R11=0100h ; The double word 01005A5Ah is now in registers R10 (10 bytes) and R11 (hi bytes) Aqke 2L CT’L) refitgeVS mm \- +w4v‘x’t . . J UJC Le (0r goob\e\ anL ‘to 1001A 44W 31"b1‘+ \O“‘3 Indirect Auto-increment Mode 2 Same as above but address in register is also incremented by 1 word or byte (depending of .W or .B) ; Assume R12 2 0330h and mem. location 0330b = 0x1234 CLR @R12+ ; Mem location 0330b = 0 and R12 = 0332b ; Now if we use the byte suffix .b CLR.B @R12+ ; Mem location O332h = O and R12 = 0333h ...
View Full Document

This note was uploaded on 10/27/2008 for the course ECE 2801 taught by Professor Jarvis during the Fall '08 term at WPI.

Page1 / 8

lect18_notes - Foundations of Embedded Systems A Term Fall...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online