lect9_notes

lect9_notes - Foundations of Embedded Systems A Term Spring...

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Unformatted text preview: Foundations of Embedded Systems A Term Spring 2008 Lecture #9: Passing the Time: Introduction to Clocks and Timers Reading for Today: MSP430 User's Guide 4, 11 Reading for Next Class: MSP430 User's Guide 13, Notes HW #3 (on web): Due Friday 9/19/2008 Lab #1 (on web): Due Tomorrow 9/16/2008 Lab #2 (on web): Due Tuesday 9/30/2008 This Class: Systems clocks and measuring the passage of time in embedded systems MSP430F449 Peripherals -- The “Standard Options” .1 6 Digital 10 Ports ./ Hardware Multiplier (used by default in C for *) FLL/System Clock module —> today 3 Timers ADC (8 channel 12 BIT) 2 USARTS (SP1) Comparator Op Amps Flash memory controller LCD Controller DMA controller >> Program control and operation of most of these peripherals is similar -— One or more Control Registers ~ — L‘t kg —P S SE L 0 ( TEE D I R - ' ' -— One or more Data Registers ' - '? 1 O UT 0 F ? (cl U I eJ-c. (Ho) MULTlPLy RE5151€Y$ Rem-+11, RESLO —— All are memory mapped '135'D1R .«_—> aggress (50st prey :> Adcbress 0:3ch All register names and even control bit names are already defined in msp430x4xx.h -- Read from and write to register names as if they were C variables! —— Will NEED to refer to MSP430 User's Guide and Data Sheet to determine how to configure each specific peripheral => “0 Single. Cot/wp‘tsdracl-lon par :9 M us+ \oo KNJ? COAVEH‘P‘OHS aged b3 0012 CJ'LK‘P Let‘s take a quick look at the Hardware Multiplier... / microF/0C€SSO/54 #include "msp430x44x.h" // Definitions, constants, etc for msp430F449 #include <stdio.h> #include <stdlib.h> #include <in430.h> void main(void) S C M (3 le L ProaerM { //declare variables in M 5 P ‘43 OFLI q 9 int a,b,c; WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer a 71; b 24; c = a*b; // IAR C compiler invokes assembly meu116 function // Can see this in Disassembly window in Kickstart II I. while (1) a = a; H W Multiplier is used by writing operands to certain addresses (memory mapped) and reading results from different addresses (defined in msp430x44x.h) \‘fih Figure 7-4. Hardware Muflipffer Biock Diagram >IAQ cl 065 ~H'f‘s g C COM 9'. Jew or US' Lao/L 4"” VD‘iSasseMbly/ ~_- Ms ME Regfifir MPY - 505w" MACS “9Y5 ' MipY. MF‘YS‘ " MAC. MACS 32—12%: Mmexa Multiplexer 15 r C 31 m M B 0P1 Address Register Name Operaiian m 30h MFY Unsigned my aiBEh MPYS Siwed multiply @134h MAE; Unsigned moifipéy mumulaie 313% MASS Sigsed multiply aemnlate 0138h 0P2 Second Operand >> First, write operand 1 to proper register (MPY, MPYS, etc) to select mode >> Then, write operand 2 to 0P2 register (address = 0138h) to initiate multiply >> Read results from RESHI, RESLO yaw?“ Came back *0 / HM) MolJr“\Pl‘iew ‘m “fie” wadd‘ MSP430F449 Clock System >> Microcontroller and peripherals are synchronous sequential logic circuits! —— Need to be clocked ;.3V : V“ «——-~ -->Before it can do ANYTHING, a CPU must h . J‘LJNJ‘LI‘L c L k ave power and a clock signal CPU >> What does a CLOCK signal look like? =7 5 ct. uaxe w a v C 35Vm p°l Sta-we'lric W m (_______4. w . Lib—JP ea“ 61"“) (LR Que: X3 >> CPU clock provides the system's time reference CLK =>T‘\me«rs (ARM/um MSPHBO (or oyxer MP) Cow/xi” c\o¢l< caches +0 MflLSUfe' elapse} +1 Ame. >> MSP 430's FLL+ Clock module —— “Full—featured and Capable” (read “Complex and Confusing”?) —— Has ability to use any of 3 possible Clock sources LFXTICLK = LF Cvflsld (LooktmS in Sol/IQMCCRCB :9 3.2 7% H2 graph}, 1; ke 44mg usel in waldos XTZCLK : HF “33de => <6 MHz er‘jsla/O DCOCLK - i peg 050%er => Inlet/“49‘ bxgxw‘ 50”“! 0,031+ >> Provides 4 clock signals to CPU and peripherals (all software selectable!) ACLKzzAuxillaryClock —_- L_F XTACLL< :3 ajéfiguq —) useé Bad Per“. (shards MCLK 2 Main or Master Clock —> CPU clock am use «not a"? 3 SourceS 3ZkHe-lo‘iéf‘l/1/z SMCLK: Sub-main Clock & b » L U$~e v.6 —><.om use New: M XTZC ‘4 30%“ (inflamed/s) ACLK/n = Buffered Clock Output 9 Pro v'iées CLOc k *‘ro {4&6va Gigi/3c e s (In >> Clock sources/speeds for CPU and peripherals are SOFTWARE selectable during RUNTIME/ :PKTl/fis (flggfee 03- CLOC/< C0A~£‘.63Ufa,l0;(¢“‘~3 i—> USUQ/QJL‘U have 1 Clock crgsflfl =l,z,\l,g§ FLU» Clock Moduie Regisiers SCFQCTL, System Clock Control Register 1" Ox I F T 6 5 4 3 2 1 D ECFQJH N ' "w-Ct rw—S rw-D rw—1 rw-i rw—1 rw—1 rw—i 2 O O I I \ \ i ' WW SCFCLM Bit 7 Moduiaiien. This enabies m disabies rmduiatim —) G Modulaiion enabled 1 Malawian disabled N Bits Multiplier. These mis get the muiiiplier value forthe DCQ. N must be I» 0 Gr 6-0 ungradictabie aperation wiil result“ When fDCQCLK: + ' fcmmi N 1: 3 ‘ When DCOPLUS=1i imw = D x (N + ‘1} - fm, SCFIO, System Clack Frequency Integrator Register 0 ; L} O h 7 a 5 4 3 2 1 o E — :w-D m—i z'w-Ci rw-D rw-O rw-S NI—U m—C’: O i O O O O O O FLLDx Bits FLL+ loop divide: These bits divide chQCqu in the FLL+ feedback loop. 16 This reams in an aciditicmal mufiipéier fur the mufiipiie: bits, See alga multi— plier mm. [K] H 481 f2 10 i4 11 f8 FN_x Bits DOD Range Eontroi. These bits select the face operating range. 1. 96068 0.55 - 831 MHZ B061 13-121MHZ 601x 2 — 119 MHZ 61.1% 2.3 - 266 MHZ 1m»: 42 — 46 MHZ MUD): Bits Least significant modulator bits. Bit 8 is the moduiatar L88. These hits 1—D affect the moduiaiof pafiem. Ail M002: bits are modified aummaticaily by me FLU. SCFH, System: Clock Frequency Integrator Register ’1 2 7 q [4 fx a 5 4 3 2 1 o E m rw—G rw—‘D M-D rw-D rev-Cl rw—D Nit-{l Ew-D O \ l \ l O O ‘ Dr:in BitS Yhese bits select the D00 tag and are modified automaticaliy by the F L1.+. 7-3 MODx Bit 2 Most significant modutator mas. Bit 2 is the ntodmator MSB. These Dita af- fect the modulator pattemm All MOD): bits are modified automattcaily by the FLU. 312,va \oL3 "FLL CichC‘t' FLU» 6100!: Module Registers "” FLL_CTLI3, FLL+ Contml Regiater 0 De .C a U l t- ; O r 3 5 s3 3 2 1 o Emil w m—D pair—S writ rw—t] rt} {'0 r-(tj r—1 0 O O o O O O o 1‘ Nat present in MSF’430:413<. MSF'4'3’JX421 devices DCOPLUS Bit 7 DEC) output pro-divider. This bit setects if the SCO output is pro—divided before soumim; MCLK or SMCLK. The division rate is seiected with the FLL_DEV hits a lit ECO output is oivioed 1 DEC output is not divided XTS_F LL Bit 6 LFTX1 mode select —) 6 Low frequency mode 1 High frequency We XCAPxPF Bits Qsciiiator capacitor seiectlon. These bits select the effective tapacitznce 5—4 seen by the LFXT‘E crystal or resonator when XTS_FLL : 0. —§ 00 wt pF ()1 ~13 pF 10 ~53 pF 11 ~10 p? XTEO‘F Bit 3 XT2 oscillator fautt. Not present in M8P43Dx41x, MSthBDxdzx devices, ‘fi G No fautt condition present 1 Fault condition present XTTUF Bit 2 LFXTt high frequency oscillator fault ‘fi i} No fault condition present 1 Fault concfiition present LFOF Bit 1 LFXT’E tow frequency osciitator fauEt a I} No fault condition present 1 Fault condition present DCDF Bit G 000 oscillator fault " G No fault condition present 1 Fautt condition present De ¥a_u\+= 0x20 FLL__CTL1, FLL+ Controf Register 1 :r a 5 a: 3 2 1 r; l Unused l SEEP SEmut SELst FLL_DIVX {B rCI wt, 3) run-{D} nut-(Cl) not—(D) nine—{fl} rw—(D‘? O O l 0 O O O O T Not present in Iv ESP-4363:4131. M853430>c42x devices. Unused Bit 2' SMCLKOFF Bit 6 SMC-LK off. This bit turns off SMCLK. Not present in MSP430x41x, MSP‘X42x devices. -—9 0 SMCLK is on 1 SMCLK is of! XTZDFF Bit ‘5 XT2 off. This bit turns off the .XTZZ osciilator. Not present in MS P430x41x, MS PX42X devices. 0 XT2 is on k>1 XT2 l5 off if it is not used for MC-LK or SMCLK. SELMK Bits Select MCLKt These him select the MCLK Source. Not present in 4 —:s MSF’430X41 x1 MSP430x42x devices. —-> 00 DCOCLK D‘t DCOCLK 10 XTZCLK 11 LFX‘H CLK SELS Bit .2 Select SMCLK. This Ni selects the SMCLK source. Not present in E‘a‘fSF’43Cbc4‘txx MSF‘430X42x devices. 0 DCOCLK 1 xmcuc FLL__DW’X Bits ACLK divider 1-0 409 11 m 12 10 :4 11 f8 tE‘f, Interrupt Enabie Register 1 | '7 l a L5 L‘lalzljfi: El Bits These bits may be used by other modules. See device-snacific uatasheet. 7—2 OFIE Bit 1 - 'll torugggit rigggnlggt @139ng This bit enables the OFIFG interrupt. Because Either bits in IE1 maybe used for other anytime-a ii: is» recommended to set or clear this nit using BIS . B or BIC . B instructions, rather than NOV . E or CLR . B instructions. D Interrupt not enahted 1 Interrupt enabled Bits D This bit may be used by other moaulesu See device-specific. datasheet. 31:61, Interrupt Flag Register 1 T l FETET ‘1 3 [—2 raft] Bits. These bits may be used by Othef modules. See device-specific damsheet. ?—2 OFIFG Bit ‘I Qscznator fault interrupt flag; Because other bits in iFG1 may be used for other modifies, it is recm1n1endaéd to set or clear this bit using BIS . B or BIC.b instructions, rather than Mov . B or CLR . E instrncfiona. O No interrupt pending 1 lnterruo! pending Bits G This hit may be used lny other modules. See device-specific datasheet Ex. What are the default settings for our '430 system on Reset? ‘ \ SCFQCTL 2 System CLK Control Register => IF hex = 0001 ll 11: I n N 1 . . scp _M=O; l Clock‘so") Q MOJU\0Qi-\Ov‘\ finaloleci. fins 35 $0041 IV; 31 ‘ : N+‘ ca.“ be LA:thch DCO ’PLLz§;Q Then 90cm“ L 3* {cr‘ésfid 0" X'VlCLK ‘ n SCFIO = Systems CLK Integrator Register 0 => 40 hex = MPG 0000 FLL DX:O\ = :2 <: ‘l’lms 15 D in calculdtms CDCOCI—K FM_X : Oooo :— 0.b§ ~Ql MHa MOD” : 00 : 3e 1‘ bug FL). ClrcuH SCFII = Systems CLK Integrator Register 1 => 79 hex = 0111 1001 Se-i FLL CWFCUX‘P FLL_CTLO = FLL Control Register 0 = 0 hex = 0000 0000 DCO PLuiS: O (Seé tuba/“2‘B XTS~FLLSD —_ Ll: MODE :05}; LV— xrAL: 3:176? 14-2 XCA’PyPF = 00 : ~ \ pl: Capacllamcé (:29er 5&5 are {QUH $44,105, 10713 FLL_CTL1 = FLL Control Register 1 = 20 hex = 0010 0000 SlACLt<0flflp _: O 1:, CLK ‘15 OH! WLOFF :\ :. XTZ Crflfilcd} 15 gm: (“0+ Using so “tom'tl 0W3 gELMx :00:MCL\<:. bco LL,,K~'— 32*31796': 1.0% MHE SE-L S o : SMCLK: DCO CLK: ltOHMHra— FLL-DN ; 00 : ACLK/n : ACLK/l \l So by default SMCLK = MCLK and both use DCO CLK as their source ACLK = Auxillary Clock = LFXTlCLK = 32768 Hz MCLK 2 Master Clock (CPU) = 32*LFXT1CLK = 1.048567 MHz SMCLlK : Sub-main Clock = DCOCLK = 1.048567 MHz ACLK/in = ACLK . C __ W MLL— M0. V0 TIMERS —- Ag: peripherals that count clock ticks, that's all. P¢O¢Q$ sors l/IGL" €- ( >> Stores the current count in register w1th1n the timer For +‘imer B ‘H-‘RS ’ts *Her TER >> Can operate in a number of common modes —- Up mode = Count from 0 to some user defined MAX COUNT , resets to O and counts again continuously until stopped ka-cw_ ' ‘ N {I = MAKJZUTX! (:o_ = 'é M MA ¥_C.NT K IUT O _ ‘/ / 6"” -— Continuous Mode 2 Count from 0 to timer's full count (like OFFFFh), 0‘ F F F Pk resets to 0 and counts continuously until stopped ' b «6 : FFFFk-{r'fiCLK 4’" 83+ /1/ INT —- Up/Down mode = Counts up from O to timer's full count (like OFFFFh) and then counts down to 0 and repeats “a elm - 3., FFFFhé= 33+ >> Timers can be polled (count register) or generate interrupts / no+ Usomilg “Eu FFl‘z“ SHAH cn+ ...
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This note was uploaded on 10/27/2008 for the course ECE 2801 taught by Professor Jarvis during the Fall '08 term at WPI.

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lect9_notes - Foundations of Embedded Systems A Term Spring...

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