lect5_notes

lect5_notes - Foundations of Embedded Systems A Term Fall...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 4
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 6
Background image of page 7
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Foundations of Embedded Systems A Term Fall 2008 Lecture #5: The MSP430F449 Memory Map and Basic Digital I/O Reading for Today: MSP430x4xx User Guide Ch 9 Reading for Next Class: MSP430x4xx User Guide Ch 9 Homework #1 (on Web): Due NOW! Homework #2 (on Web): Due 9/11/2008 in class Lab #0 (on web): Report due 9/9/2008 in class Last class: An overview of the architecture of the MSP430F449 microprocessor >> MSP430 family uses a Von Neumann architecture. >> Its memory is byte addressable and 'F449 has 2KB RAM, 60KB Flash, and many on-Chip peripherals (System—on-a—Chip) This class: Specifics of the MSP430F449 memory organization ————_“____—_— Memory Map for MSP43OX44X Processors (from User's Guide Ch 1) Access DFFFFh ‘ I interrupt Vector Table Word/Byte OFFEflh OFFDFh word/Byte Hash/ROM 31FFh ' _ man DFFh . _ UFh >> RAM starts at 0200b what is the last address in our 2KB RAM? '0 _ Q kg Ls readilj Q \<'s\o b‘tnafg I Q *3 = «2 *mlq‘zoqg b‘J‘LeS >> What are the addresses for our 60KB of Flash (ROM)? ‘3? Fluke EMA/O out flFFFFA (I'Vlev‘rup—l Veal-or R5 sloweé In Flash) 3) éOKes (00¢: \oqujieS: F¢€0¢k .:)Fla,§l\ 60% “hem \oook +0¢FFFFk Wm— :7Coée -\Swrl‘\‘l’€v\ +0 FLASH when (you program,1 “Me— MS-PqSO F/Lotm Ila-R Ric/{5+4r‘t‘ >> Additionally, inside the CPU, there are sixteen 16—bit register : 3'22 >> Registers R0—R3 have dedicated functions 4: (—1; (A ,. s2. *Useé 5‘3 \< [20: T’Drofiram Coomler (U561 4‘) LASWUChOAs 'lro CPU 40"” Ensth poln‘ler am [Exéwfim‘ 9’03“ R2,: slat/40$ ( R3: COR$+LLW-l€ genera/410m >> Registers R4 — R15 are user registers —— Like scratch pad for data values being used by current or recent instructions —— Retrieving an operand from a CPU register is much more efficient than reading it in from memory -- IAR Kickstart C compiler tries to maximize register use >> Whats the deal with the addresses 0010h-01FFh assigned to peripherals? MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLA8344D — JANUARY 2002 — REVlSED AUGUST 2004 module enable registers 1 and 2 Address 7 6 5 4 3 2 1 0 UTXEO URXEO / nN—O rw—O URXEO: USARTO: UART mode receive enable UTXEO: USARTO: UART mode transmit enable USPIEO: USARTO: SPI mode transmit and receive enable Address 7 6 5 4 3 2 1 0 rw—O rw—O URXEi: USART1: UART mode receive enable (MSP430F44X devices only) UTXE1: USART1: UART mode transmit enable (MSP430F44X devices only) USPlE1: USART1: SPI mode transmit and receive enable (MSP430F44x devices only) Legend: rw: Bit Can Be Read and Written I'W-0,1= Bit Can Be Read and Written. It Is Reset or Set by PUC. l'W-(011)= Bit Can Be Read and Written. It Is Reset or Set by FOR. C: SFR Bit Not Present in Device MSP430 F437 MSP430 F435 MSP430 F436 M s P 43°F 4 47 MSP430 F448 MSP430 F449 60KB memory organization Memory Main: interrupt vector OFFFFh — OFFEOh OFFFFh - OFFEOh OFFFFh — OFFEOh OFFFFh — OFFEOh OFFFFh — OFFEOh Main: code memory OFFFFh -— OCOOOh OFFFFh — OAOOOh OFFFFh — 08000?) OFFFFh — 04000h OFFFFh — 01100h / Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte 256 Byte Flash 010FFh — 01000h 010FFh - 01000h 010FFh — 01000h 010FFh — 01000h 010FFh — 01000h Boot memory Size 1 KB 1 KB 1 KB 1 KB 1 KB ROM OFFFh — OCOOh OFFFh — OCOOh OFFFh — OCOOh OFFFh — OCOOh OFFFh — OCOOh RAM Size 512 Byte 1KB 1KB 2KB 2KB 03FFh —- 0200h 05FFh — 0200h 05FFh — 0200h 09FFh — 0200h 09FFh — 0200h Peripherals 16-bit 01FFh — 0100h 01FFh — 0100h 01 FFh — O100h 01FFh — 0100h 01 FFh —- 0100h 8-bit OFFh — 010h OFFh — O10h OFFh — 010h OFFh — 010h OFFh — 010h 8-bit SFFi OFh — 00h OFh — 00h OFh — 00h OFh — 00h OFh — 00h I RAM bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user—defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAAO89. BSL Function PN Package Pins PZ Package Pins Data Receive 66 - P1.1 86 - P1.1 {5‘ TEXAS INSTRUMENTS 16 POST OFFICE BOX 655303 . DALLAS, TEXAS 75265 Almost all computer programs require Input and produce Output... >> Consider this C code for a General Purpose computer #include <stdio.h> void main() { char inKey = '—'; // declare variable named inKey // and initialize it to be '—' while (inKey != 'X'); { /* get character from keyboard */ inKey = getchar(); /* display character entered on screen */ putchar(inKey); } } How is the Input and Output handled? It's just a simple bit of software? >> getchar( ) and putchar( ) are C functions and part of the stdio library >> Their function prototypes can be found in stdio.h >> These “canned” software routines have always been part of standard C because everybody using general purpose computers has needed to read characters from a keyboard and write to a monitor! --> Several computing “layers” below our simple little application a byte has been placed on the microprocessor's data bus from the PORT attached to the keyboard... ?\fi-cko~r(\ '3' 6€+ MIC) =C Ponc‘iious P503” A Ssem bus ‘- MDV 9L, p011” ; From ?0r+n mOV 'Pok’i'tsJ AL. To -Fo/*. g Embedded Systems are Application-Specific and Unique >> There isn‘t a nominal configuration for a MSP430 based computer uw L o? messes 3M Lixx Liky €>0Ver LID proceSSors In all :5) 6L“ have d‘t$FereV\t memonfi' +‘Pav-1Pheml cow-y‘flvv‘kfim =3 Digs-‘QWJF gjsiewxs \rxcwe C1,‘\Qi:eren‘i' HM) connec‘i‘eé +0 ‘i/KQ processor Cannec‘i‘eé- +0 6‘“ LED: 0\ bu++0m bome‘ufl‘iws else, Ao+k1n<3 Cd 1“ 1». I —--Is ’Povcx's em 1. 9 No presei' Ccmveni-‘HMS >> TI can‘t supply canned I/O routines* because the I/O varies so much! (*Embedded OS are starting to provide some “system call” functionalities) >> Embedded Systems Designer decides what 1/0 the system needs wfimgcr‘dwe Sensor or R ? Ln‘ie r a 4-1- >> System designer integrates the HW sensors directly with uP’s I/O ports page or 50% ——> Those ports and peripheral provide the “P with input/output capabilities --> In the MSP430 the peripherals and ports are Memory Mapped =>Tlxeir aééresscs acre. ’Par‘i' 0‘: +k€ Memorfl I‘léclveSS SEDCKC ‘2 .-=) In 9613430 Address 00”? ‘0‘ FF“ >> Most modern microcontrollers and even general purpose micro—processors will have at least some of these “standard gptions” peripherals on—chip >>Digital I/O, timers, interrupt controllers, USART, ADC, comparators,.. >> The tricks is figuring out how they work on YOUR specific chip! MSP430F449 Basic Digital 1/0 —> U\5.~\a\ 1/0 —' ReaAmS w wiri‘lmfi Mémdm ‘29}{5 ‘l’c‘l‘me pms 0L >> Six independent, individually configurable digital I/O ports >> Each port is 8 bits wide >> Each pin of each port can be configured individually as input or output >> Each pin of each port can be individually read from or written to >> Ports 1 and 2 can generate interrupts which are control signals that can be accepted or ignored by the '430 -— We'll be using interrupts later in the term >> Each port is controlled by 4 byte-addressable (i.e. 1 byte wide) registers >> All the I/O port registers are memory mapped meaning each register associated with an 10 port or other peripheral device has a unique address 'voa c 007 => moor Q-OBSh ’Pod 5 Se\ecl- => VBSEL = OOH?“ How do you know what the addresses are? U ==> Look Ln Ms?qsquuq DATASHEET<I°JZ“) /_ . 0x”x¥.h —- - +0 addresses In msPL'S '9 flHSoI NAMes are QSScfifleé The 4 registers controlling the Digital I/O ports are Function Select Register: 33 lea-L5 \HqCL-lr fiber-t» ‘Fo r M mos“. 'PW‘S CCU“ have 1 or More canal-30V“; PXSEL (19- 1’3 SEQ \ =- (PerXleeraJ or Fanc‘hOn MD A?- (D : ty\%d'*QJ :I:}o passe: // 39+ «I p _ // Par-('3 {10” Al%'+‘J (1/0 @Z 55:. : OXFO; //Se/ec+ b;+ 0—3 0?- For+z ’l/ hr diji-hf SE/g DirectionRegister: Sds ?“ns as an? 0+ 0v. 00+Purf- who} Aces ’?HD\R= 0x0 F; 40? (?1ns O-3:oo+pa’* «AA 'Pins (4.“) Mg Cnpd‘t‘sx Input Register: N 'PQIN 1 a a Inpu+ VGJQXW W QWW mééress Output Register: ’\ , ,_ (\MO‘J PL! OU l V0944“ +0 52 OO+OU_* are, LorrHen 4—0 W miéress /PSOUT : MbOo‘i’Vatluc; Using the digital I/O ports is conceptually simple... =>\)Jr‘\\e or fecal \chKUES *0/‘p’0‘m ’Pork— (ecs‘csiev‘ names as defined 1“ >> Make extensive use of C‘s Bitwise operations -- & | ~ (and &= I: ~= ...
View Full Document

This note was uploaded on 10/27/2008 for the course ECE 2801 taught by Professor Jarvis during the Fall '08 term at WPI.

Page1 / 7

lect5_notes - Foundations of Embedded Systems A Term Fall...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online