74HC138 - INTEGRATED CIRCUITS DATA SHEET For a complete...

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DATA SHEET Product specification File under Integrated Circuits, IC06 September 1993 INTEGRATED CIRCUITS 74HC/HCT138 3-to-8 line decoder/demultiplexer; inverting For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
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September 1993 2 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138 FEATURES Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Active LOW mutually exclusive outputs Output capability: standard I CC category: MSI GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT138 decoders accept three binary weighted address inputs (A 0 , A 1 , A 2 ) and when enabled, provide 8 mutually exclusive active LOW outputs ( Y 0 to Y 7 ). The “138” features three enable inputs: two active LOW ( E 1 and E 2 ) and one active HIGH (E 3 ). Every output will be HIGH unless E 1 and E 2 are LOW and E 3 is HIGH. This multiple enable function allows easy parallel expansion of the “138” to a 1-of-32 (5 lines to 32 lines) decoder with just four “138” ICs and one inverter.
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74HC138 - INTEGRATED CIRCUITS DATA SHEET For a complete...

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